LXT9761/9781
Fast Ethernet 10/100 Multi-Port Transceiver with RMII
Datasheet
The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical
layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent
Interface (RMII) for switching and other independent port applications. The LXT9761 offers the
same features and functionality in a six-port device. This data sheet uses the singular designation
“LXT97x1” to refer to both devices.
All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for
a 10/100BASE-TX or 100BASE-FX connection.
The LXT97x1 provides three discrete LED driver outputs for each port, as well as eight global
serial LED outputs. The device supports both half- and full-duplex operation at 10 Mbps and 100
Mbps, and requires only a single 3.3V power supply.
Applications
s
100BASE-T, 10/100-TX, or 100BASE-FX
Switches and multi-port NICs.
Product Features
s
s
s
s
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Six or eight IEEE 802.3-compliant
10BASE-T or 100BASE-TX ports with
integrated filters
3.3V operation
Optimized for dual-high stacked R45
applications
Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over
ideal analog filters
Robust baseline wander correction
100BASE-FX fiber-optic capability on all
ports
s
s
s
s
s
s
s
s
Supports both auto-negotiation and legacy
systems without auto-negotiation capability
JTAG boundary scan
Multiple Reduced MII (RMII) ports for
independent PHY port operation
Configurable via MDIO port or external
control pins.
Maskable interrupts
Low power consumption (390 mW per
port, typical)
208-pin PQFP (LXT9761 and LXT9781)
272-pin PBGA (LXT9781 only)
As of January 15, 2001, this document replaces the Level One document
LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII.
Order Number: 249048-001
January 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT9761/9781 may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................21
2.1
Introduction..........................................................................................................21
2.1.1 OSP™ Architecture ................................................................................21
2.1.2 Comprehensive Functionality .................................................................21
Interface Descriptions..........................................................................................22
2.2.1 10/100 Network Interface .......................................................................22
2.2.1.1 Twisted-Pair Interface ...............................................................22
2.2.1.2 Fiber Interface ...........................................................................23
2.2.2 RMII Interface.........................................................................................23
2.2.3 Configuration Management Interface .....................................................23
2.2.3.1 MDIO Management Interface ....................................................23
2.2.3.2 Hardware Control Interface .......................................................25
Operating Requirements .....................................................................................25
2.3.1 Power Requirements..............................................................................25
2.3.2 Clock Requirements ...............................................................................26
2.3.2.1 Reference Clock ........................................................................26
Initialization..........................................................................................................26
2.4.1 MDIO Control Mode ...............................................................................26
2.4.2 Hardware Control Mode .........................................................................26
2.4.3 Power-Down Mode.................................................................................27
2.4.3.1 Global (Hardware) Power Down................................................27
2.4.3.2 Port (Software) Power Down .....................................................27
2.4.4 Reset ......................................................................................................28
2.4.5 Hardware Configuration Settings ...........................................................28
Link Establishment ..............................................................................................29
2.5.1 Auto-Negotiation.....................................................................................29
2.5.1.1 Base Page Exchange................................................................29
2.5.1.2 Next Page Exchange.................................................................29
2.5.1.3 Controlling Auto-Negotiation .....................................................29
2.5.2 Parallel Detection ...................................................................................30
RMII Operation ....................................................................................................30
2.6.1 Reference Clock.....................................................................................31
2.6.2 Transmit Enable .....................................................................................31
2.6.3 Carrier Sense & Data Valid ....................................................................31
2.6.4 Receive Error .........................................................................................31
2.6.5 Loopback................................................................................................31
2.6.6 Out of Band Signalling............................................................................31
2.6.7 4B/5B Coding Operations.......................................................................32
100 Mbps Operation............................................................................................32
2.7.1 100BASE-X Network Operations ...........................................................32
2.7.2 100BASE-X Protocol Sublayer Operations ............................................33
2.7.2.1 PCS Sublayer ............................................................................33
2.7.2.2 PMA Sublayer ...........................................................................35
2.7.2.3 Twisted-Pair PMD Sublayer ......................................................36
2.7.2.4 Fiber PMD Sublayer ..................................................................37
2.2
2.3
2.4
2.5
2.6
2.7
Datasheet
3
LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
2.8
2.9
2.10
10 Mbps Operation.............................................................................................. 37
2.8.1 Preamble Handling................................................................................. 37
2.8.2 Dribble Bits............................................................................................. 38
2.8.3 Link Test................................................................................................. 38
2.8.3.1 Link Failure................................................................................ 38
2.8.4 Jabber .................................................................................................... 38
Monitoring Operations......................................................................................... 38
2.9.1 Monitoring Auto-Negotiation................................................................... 38
2.9.2 Serial LED Functions ............................................................................. 38
2.9.3 Per-Port LED Driver Functions............................................................... 40
2.9.3.1 LED Pulse Stretching ................................................................ 40
2.9.4 Using the Quick Status Register ............................................................ 41
2.9.5 Out-of-Band Signalling ........................................................................... 42
Boundary Scan (JTAG1149.1) Functions ........................................................... 42
2.10.1 Boundary Scan Interface........................................................................ 42
2.10.2 State Machine ........................................................................................ 42
2.10.3 Instruction Register ................................................................................ 43
2.10.4 Boundary Scan Register ........................................................................ 43
Design Recommendations .................................................................................. 44
3.1.1 General Design Guidelines .................................................................... 44
3.1.2 Power Supply Filtering ........................................................................... 44
3.1.3 Power and Ground Plane Layout Considerations .................................. 45
3.1.3.1 Chassis Ground......................................................................... 45
3.1.4 RMII Terminations .................................................................................. 45
3.1.5 The RBIAS Pin ....................................................................................... 45
3.1.6 The Twisted-Pair Interface ..................................................................... 46
3.1.6.1 Magnetics Information ............................................................... 46
3.1.7 The Fiber Interface................................................................................. 46
Typical Application Circuits ................................................................................. 46
3.0
Application Information
......................................................................................... 44
3.1
3.2
4.0
5.0
6.0
Test Specifications
.................................................................................................. 52
Register Definitions
................................................................................................ 62
Package Specifications
......................................................................................... 77
4
Datasheet
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
Figures
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LXT9781 Block Diagram ....................................................................................... 9
LXT9781 PQFP Pin Assignments .......................................................................10
LXT9781 PBGA Pin Assignments ......................................................................11
LXT9761 PQFP Pin Assignments .......................................................................12
LXT97x1 Interfaces ............................................................................................22
Port Address Scheme .........................................................................................24
Management Interface Read Frame Structure ...................................................24
Management Interface Write Frame Structure ...................................................24
Interrupt Logic .....................................................................................................25
Initialization Sequence .......................................................................................27
Hardware Control Settings .................................................................................28
Auto-Negotiation Operation ................................................................................30
Loopback Paths ..................................................................................................31
RMII Data Flow ...................................................................................................32
100BASE-X Frame Format ................................................................................33
Protocol Sublayers .............................................................................................34
Serial LED Streams.............................................................................................39
LED Pulse Stretching ..........................................................................................41
Quick Status Register..........................................................................................41
RMII Programmable Out of Band Signalling .......................................................42
Power and Ground Supply Connections ............................................................47
Typical Twisted-Pair Interface ............................................................................48
Typical Fiber Interface ........................................................................................49
Typical RMII Interface ........................................................................................50
Typical Serial LED Interface................................................................................51
100BASE-TX Receive Timing ...........................................................................55
100BASE-TX Transmit Timing ..........................................................................55
100BASE-FX Receive Timing ...........................................................................56
100BASE-FX Transmit Timing ..........................................................................57
10BASE-T Receive Timing ................................................................................57
10BASE-T Transmit Timing ...............................................................................58
Auto-Negotiation and Fast Link Pulse Timing ...................................................59
Fast Link Pulse Timing .......................................................................................59
MDIO Write Timing (MDIO Sourced by MAC) ....................................................60
MDIO Read Timing (MDIO Sourced by PHY) ....................................................60
Power-Up Timing ................................................................................................61
RESET And Power-Down Recovery Timing ......................................................61
PHY Identifier Bit Mapping .................................................................................67
LXT97x1 PQFP Specification .............................................................................77
LXT9781 PBGA Specification .............................................................................78
Tables
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3
4
5
LXT97x1 RMII Signal Descriptions......................................................................13
LXT97x1 Signal Detect/TP Select Signal Descriptions .......................................15
LXT97x1 Network Interface Signal Descriptions .................................................16
LXT97x1 JTAG Test Signal Descriptions ............................................................16
LXT97x1 Miscellaneous Signal Descriptions ......................................................17
Datasheet
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