73S8009C
Versatile Power Management
and Smart Card Interface IC
Simplifying System Integration™
DS_8009C_025
DATA SHEET
January 2010
When power is supplied by V
PC
or V
BAT
, the
73S8009C is controlled by the ON_OFF pin in the
manner of a “push-on/push-off” button action. The
signals OFF_REQ and OFF_ACK provide
handshaking and control of the power “off”
function by the controller. A SPST momentary
switch to ground connected to ON_OFF is all that
is required for power control. Alternatively, the “off”
state can be initiated from the host controller
through OFF_ACK. When the 73S8009C is “off,”
the current is less than 1
µA.
When power is supplied via the V
BUS
pin, the
73S8009C is unconditionally in the “power-on”
state regardless of the action of the ON/OFF
switch or OFF_ACK signal. Power supply current
operating from the V
BUS
power when V
CC
is off is
less than 500
µA
to conform to USB “SUSPEND”
requirements.
APPLICATIONS
•
•
•
Handheld PINpad smart card readers for
e-commerce, secure login, e-health, Gov’t ID
and loyalty
Point of Sales & Transaction Terminals
General Purpose Smart Card Readers
DESCRIPTION
The Teridian 73S8009C is a versatile power
management and single smart card interface
circuit that is ideally suited for smart card reader
products that are battery and/or USB bus-
powered. In addition to its EMV 4.1 and
ISO-7816-3 compliant smart card-to-host interface
circuitry; it provides control, conversion, and
regulation of power for a companion host
processor circuit and power for the smart card.
The 73S8009C can operate from a single 2.7 V to
6.5 V source supply, or a combination of battery
power (4.0 V to 6.5 V) and USB power (4.4 V to
5.5 V).
The 73S8009C supports 5 V, 3 V, and 1.8 V smart
cards. The smart card signals for RST, CLK, IO,
and auxiliary signals AUX1 and AUX2 are
level-shifted to the selected V
CC
value. Although
the host controller is required to handle the
detailed signal timing for activation and de-
activation under normal conditions, the 73S8009C
blocks any spurious signals on CLK, RST and IO
during power-up (as V
CC
rises) and power-down.
The 73S8009C contains two handshaking signals
for the controller:
OFF
indicates that a card is
present, and RDY indicates that V
CC
is at an
acceptable value. The 73S8009C will perform
emergency deactivation upon card removal,
voltage faults, or over-current events
The power management circuitry of the 73S8009C
allows operation from a wide range of voltages
from multiple sources. V
PC
is converted by using
an inductive, step-up power converter to the
intermediate voltage, V
P
. V
P
is used by linear
voltage regulators and switches to create the
voltages V
DD
and as required, V
CC
. V
DD
is used by
the 73S8009C and is also made available for the
companion controller circuit or other external
circuits. The two pins, V
BAT
and V
BUS
provide
inputs from alternate power sources as required.
An internal switch in the 73S8009C acts as a
single-pole, double-throw switch that selects either
V
BAT
or V
BUS
to be connected to V
PC
. When the
voltage on V
BUS
is zero, V
BAT
is connected to V
PC
.
When voltage is applied to V
BUS
, the switch will
select V
BUS
as the source for power.
Rev. 1.4
ADVANTAGES
•
Ideally suited to USB bus-powered
applications
Ideal for combo bus-powered and/or
self-powered systems
Automatic battery switchover in bus
powered systems
•
Very low-power mode (sub-µA) with
push-button ON/OFF switch input with
de-bounce
Provides 3.3 V / 40 mA power to external
circuitry (host processor or peripheral circuits)
The inductor-based DC-DC converter provides
higher current and efficiency than usual
charge-pump capacitor-based converters:
Ideal for battery-powered applications
•
•
© 2010 Teridian Semiconductor Corporation
1
73S8009C Data Sheet
FEATURES
•
Smart card Interface:
•
Complies with ISO-7816-3 and EMV 4.1
and derivative standards
•
A DC-DC Converter provides 1.8 V/3 V/5 V
to the card from a wide range of external
power supply inputs
•
Provides up to 65 mA to the card
•
ISO-7816-3 Card emergency deactivation
sequencer
•
2 voltage supervisors detect voltage drops
on the V
CC
(card) and V
DD
(digital) power
supplies
•
Card over-current detection 150 mA max.
•
2 card detection inputs, 1 for either user
polarity
•
Auxiliary I/O lines for synchronous and
ISO-7816-12 USB card support
•
Card CLK clock frequency up to 20 MHz
•
6 kV ESD and short circuit protection on
the card interface
•
System Controller Interface:
•
5 Signal images of the card signals
(RSTIN, CLKIN, I/OUC, AUX1UC and
AUX2UC)
•
2 Inputs activate and select the card
voltage (CMDVCC% and
CMDVCC#)
•
2 Outputs, interrupt to the system controller
(OFF and RDY), to inform the system
controller of the card presence / faults and
status of the interface
•
1 Chip Select input (CS - QFN32 only)
•
2 Handshaking signals for proper shutdown
sequencing of all output supply voltages
(OFF_REQ, OFF_ACK)
•
ON/OFF Main System Switch:
•
Input for an SPST momentary switch to
ground
•
DC-DC Converter:
•
Step-up converter
DS_8009C_025
•
Generates an intermediary voltage V
P
•
Requires a single 10
µH
Inductor
•
System Power Supply requirements:
•
When using VBUS: Standard USB +5
input (range +4.4 V to 5.5 V)
•
When using V
BAT
: 4.0 V to 6.5 V
•
When using V
PC
: 2.7 V to 6.5 V
•
Automated detection of voltage presence -
Priority on VBUS over VBAT
•
Power Supply Output:
•
V
DD
supply output available to power up
external circuitry: 3.3 V
±0.3
V, 40 mA
Industrial temperature range
Small format QFN20 and QFN packages
RoHS compliant (6/6) lead-free package
•
•
•
2
Rev. 1.4
73S8009C Data Sheet
FUNCTIONAL DIAGRAM
CS
12
DS_8009C_025
TEST1 TEST2
10 [7]
30 [20]
VDD
29 [19]
VBAT VBUS
25
23
vref
15 [9]
24 [15]
VOLTAGE
REFERENCE
VCC FAULT
VPC FAULT
VCC OK
VCC = 5
VCC = 3
VP
S2
S1
26 [16]
bias currents
VPC
27 [17]
ON_OFF
4 [3]
LIN
SWITCH/LDO
REGULATOR
17 [11]
CMDVCC5
5 [4]
CMDVCC3
OFF
32 [1]
8
GND
19 [13]
CONTROL
LOGIC
POWER DOWN
ON/OFF
VCC
RESET
BUFFER
18 [12]
RDY
OFF_REQ
OFF_ACK
11
9
RST
RSTIN
CLKIN
6 [5]
7 [6]
1.5MHz
CLOCK
BUFFER
16 [10]
CLK
14 [8]
PRES
13
PRES
R-C
OSC.
I/OUC
AUX1UC
1 [2]
2
3
22 [14]
I/O
SMART CARD I/O BUFFERS
AND SIGNAL LOGIC
21
AUX1
20
AUX2UC
AUX2
28 [18]
GND
Pin numbers reference to the QFN32 package
[Pin numbers] reference to the QFN20 package
Figure 1: 73S8009C Block Diagram
Rev. 1.4
3
73S8009C Data Sheet
DS_8009C_025
Table of Contents
1
2
Pinout ............................................................................................................................................. 6
Electrical Specifications.............................................................................................................. 10
2.1 Absolute Maximum Ratings ................................................................................................... 10
2.2 Recommended Operating Conditions .................................................................................... 11
2.3 Smart Card Interface Requirements ...................................................................................... 11
2.4 Digital Signals Characteristics ............................................................................................... 14
2.5 DC Characteristics ................................................................................................................ 15
2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 15
2.7 Thermal Characteristics ........................................................................................................ 15
Applications Information ............................................................................................................. 16
3.1 Example 73S8009C Schematics ........................................................................................... 16
3.2 Power Supply and Converter ................................................................................................. 18
3.3 Interface Function - ON/OFF Modes...................................................................................... 18
3.4 System Controller Interface ................................................................................................... 20
3.5 Card Power Supply and Voltage Supervision......................................................................... 20
3.6 Activation and De-activation Sequence ................................................................................. 21
3.7
OFF
and Fault Detection ....................................................................................................... 22
3.8 Chip Selection ....................................................................................................................... 23
3.9 I/O Circuitry and Timing......................................................................................................... 24
Equivalent Circuits ...................................................................................................................... 26
Mechanical Drawing .................................................................................................................... 30
Ordering Information ................................................................................................................... 32
Related Documentation ............................................................................................................... 32
Contact Information..................................................................................................................... 32
3
4
5
6
7
8
4
Rev. 1.4
DS_8009C_025
73S8009C Data Sheet
Figures
Figure 1: 73S8009C Block Diagram ......................................................................................................... 3
Figure 2: 73S8009C 32-Pin QFN Pinout .................................................................................................. 6
Figure 3: 73S8009C 20-Pin QFN Pinout .................................................................................................. 6
Figure 4: Typical 73S8009C Application Schematic ............................................................................... 17
Figure 5: 73S8009C Logical Block Diagram ........................................................................................... 19
Figure 6: Activation Sequence ............................................................................................................... 21
Figure 7: Deactivation Sequence ........................................................................................................... 22
Figure 8:
OFF
Activity ............................................................................................................................ 22
Figure 9: CS Timing Definitions.............................................................................................................. 23
Figure 10: I/O and I/OUC State Diagram ................................................................................................ 24
Figure 11: I/O – I/OUC Delays - Timing Diagram.................................................................................... 25
Figure 12: On_Off Pin ............................................................................................................................ 26
Figure 13: Open Drain type –
OFF
and RDY .......................................................................................... 26
Figure 14: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP ........................................................... 26
Figure 15: Smart Card CLK Driver Circuit .............................................................................................. 27
Figure 16: Smart Card RST Driver Circuit .............................................................................................. 27
Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit................................................................. 28
Figure 18: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit.................................................. 28
Figure 19: General Input Circuit ............................................................................................................. 29
Figure 20: OFF_REQ Interface Circuit ................................................................................................... 29
Figure 22: 20-Pin QFN Package Dimensions ......................................................................................... 30
Figure 22: 32-Pin QFN Package Dimensions ......................................................................................... 31
Tables
Table 1: 73S8009C Pin Definitions .......................................................................................................... 7
Table 2: Absolute Maximum Device Ratings .......................................................................................... 10
Table 3: Recommended Operating Conditions ....................................................................................... 11
Table 4: DC Smart Card Interface Requirements ................................................................................... 11
Table 5: Digital Signals Characteristics .................................................................................................. 14
Table 6: DC Characteristics ................................................................................................................... 15
Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 15
Table 8: Thermal Characteristics ........................................................................................................... 15
Table 9: Order Numbers and Packaging Marks ...................................................................................... 32
Rev. 1.4
5
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