73K324BL
CCITT V.22bis,V.23,V.22,V.21,Bell 212A
Single-Chip Modem w/ Integrated
Hybrid
Simplifying System Integration™
DATA SHEET
JUNE 2008
DESCRIPTION
The 73K324BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bps full-duplex operation over dial-up lines. The
73K324BL is an enhancement of the 73K324L single-
chip modem, which adds the hybrid hook switch
control, and driver to the 73K324L. The 73K324BL
integrates analog, digital, and switched-capacitor
array functions on a single chip, offering excellent
performance and a high level of functional integration
in a 32-Lead PLCC package.
The 73K324BL operates from a single +5 V supply for
low power consumption.
The 73K324BL is designed to appear to the systems
designer as a microprocessor peripheral, and will
easily interface with popular single-chip micro-
processors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or via an optional serial control bus. An ALE
control simplifies address demultiplexing. Data
communications normally occur through a separate
serial port.
(continued)
FEATURES
•
•
•
•
•
•
•
•
•
Includes features of 73K324L single-chip
modem
On chip 2-wire/4-wire hybrid driver and off
hook relay buffer
One-chip multi-mode V.22bis/V.22/V.21/V.23
and Bell 212A compatible modem data pump
FSK (300/1200 bps), DPSK (600, 1200 bps), or
QAM (2400 bps) encoding
Software compatible with other
conductor K-Series one-chip modems
Interfaces directly with standard
processors (80C51 typical)
Parallel or serial bus for control
Selectable
asynch/synch
with
internal
buffer/debuffer and scrambler/descrambler
functions
All asynchronous and synchronous operating
modes (internal, external, slave)
(continued)
Semi-
micro-
BLOCK DIAGRAM
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
FSK
MODULATOR
OH
BUFFER
SCRAMBLER
DI-BIT/
QUAD-BIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
FILTER
EQUALIZER
FILTER
ATTENUATOR
TXA1
2W/4W
HYBRID
TXA2
RXA
PASS
BAND
FILTER
AGC
GAIN
BOOST
8-BIT
µP
BUS
INTERFACE
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
FILTER
A/D
DEBUFFER
DESCRAMBLER
DI-BIT/
QUAD-BIT
DECODER
EQUALIZER
ANTI-ALIAS
FILTER
FIXED
DEMODULATOR
TXD
RXD
SERIAL
INTERFACE
TONE
DETECTION
Page: 1 of 34
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
DESCRIPTION
(continued
)
The 73K324BL is pin and software compatible with
the 73K222BL and 73K224BL, allowing system
upgrades and product differentiation with a single
component change.
The 73K324BL is designed to be a complete V.22bis
compatible modem on a chip. The complete modem
requires only the addition of the phone line interface,
a control microprocessor, and RS-232 level
converter for a typical system. Many functions were
included to simplify implementation of typical modem
designs. In addition to the basic 2400 bps QAM,
600/1200 bps DPSK and 300/1200 bps FSK
modulator/demodulator sections, the device also
includes
synch/asynch
converters,
scrambler/descrambler, call progress tone detect,
DTMF tone generator capabilities and handshake
pattern detectors. Test features such as analog loop,
digital loop, and remote digital loopback are
supported. Internal pattern generators are also
included for self-testing.
FEATURES
(continued)
•
•
Adaptive
equalization
performance over all lines
for
optimum
Programmable transmit attenuation (16 dB, 1
dB
steps),
selectable
receive
boost
(+18 dB)
Call
progress,
carrier,
answer
tone,
unscrambled mark, S1, and signal quality
monitors
DTMF, answer,
generators
SCT,
and
guard
tone
•
•
•
•
Test modes available: ALB, DL, RDL, mark,
space, alternating bit, S1 pattern
CMOS technology for low power consumption
(typically 100 mW @ 5 V) with power-down
mode (15 mW @ 5 V)
TTL and CMOS compatible inputs and outputs
•
Page: 2 of 34
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
FUNCTIONAL DESCRIPTION
HYBRID AND RELAY DRIVER
To make designs more cost effective and space
efficient, the 73K324BL includes the 2-wire to 4-wire
hybrid with sufficient drive to interface directly to the
telecom coupling transformers. In addition, an off
hook relay driver with 40 mA drive capability is also
included to allow use of commonly available
mechanical telecom relays.
QAM MODULATOR/DEMODULATOR
The 73K324BL encodes incoming data into quad-bits
represented by 16 possible signal points with specific
phase and amplitude levels. The base-band signal is
then filtered to reduce intersymbol interference on the
band limited telephone network. The modulator
transmits this encoded data using either a 1200 Hz
(originate mode) or 2400 Hz (answer mode) carrier.
The demodulator, although more complex, essentially
reverses this procedure while also recovering the
data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically
changing
filter
parameters
to
compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR
The 73K324BL modulates a serial bit stream into
di-bit pairs that are represented by four possible
phase shifts as prescribed by the Bell 212A/V.22
standards. The base-band signal is then filtered to
reduce intersymbol interference on the bandlimited 2-
wire PSTN line. Transmission occurs on either a 1200
Hz (originate mode) or 2400 Hz carrier (answer
mode).
Demodulation is the reverse of the
modulation process, with the incoming analog signal
eventually decoded into di-bits and converted back to
a serial bit stream. The demodulator also recovers
the clock, which was encoded into the analog signal
during modulation. Demodulation occurs using either
a 1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or ALB
answer mode). The 73K324BL use a phase locked
loop coherent demodulation technique that offers
excellent performance. Adaptive equalization is also
used in DPSK modes for optimum operation with
varying line conditions.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space) are used in V.21
mode. V.23 mode uses 1300 and 2100 Hz for the
main channel and 390 and 450 Hz for the back
channel. Demodulation involves detecting the
received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are automatically bypassed in
the FSK modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering
corresponds to a 75% square root of raised Cosine
frequency response characteristic.
ASYNCHRONOUS MODE
The asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 bps +1%, -2.5% even though
the modem’s output is limited to the nominal bit rate
±.01% in DPSK and QAM modes. When transmitting
in this mode the serial data on the TXD input is
passed through a rate converter which inserts or
deletes stop bits in the serial bit stream in order to
output a signal that is the nominal bit rate ±.01%. This
signal is then routed to a data scrambler and into the
analog modulator where quad-bit/di-bit encoding
results in the output signal. Both the rate converter
and scrambler can be bypassed for handshaking, and
synchronous operation as selected. Received data is
processed in a similar fashion except that the rate
converter now acts to reinsert any deleted stop bits
and output data to the terminal at no greater than the
bit rate plus 1%. An incoming break signal (low
through two characters) will be passed through
without incorrectly inserting a stop bit.
Page: 3 of 34
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
FUNCTIONAL DESCRIPTION
(continued)
The synch/asynch converter also has an extended
Overspeed mode, which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at 7/8
rising edge of TXCLK the normal width.
Both the synch/asynch rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the
asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz
signal in internal mode and is connected internally to
the RXCLK pin in slave mode. Receive data at the
RXD pin is clocked out on the falling edge of RXCLK.
The asynch/synch converter is bypassed when
synchronous mode is selected and data is transmitted
at the same rate as it is input.
PARALLEL BUS CONTROL INTERFACE MODE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as seven consecutive memory
locations. Six control registers are read/write memory.
The detect and ID registers are read only and cannot
be modified except by modem response to monitored
parameters.
SERIAL CONTROL INTERFACE MODE
The serial Command mode allows access to the
73K324BL control and status registers via a serial
control port. In this mode the AD0, AD1, and AD2
lines provide register addresses for data passed
through the AD7 (DATA) pin under control of the
RD
and
WR
lines. A read operation is initiated when the
RD
line is taken low. The next eight cycles of EXCLK
will then transfer out eight bits of the selected address
location LSB first. A write takes place by shifting in
eight bits of data LSB first for eight consecutive
cycles of EXCLK.
WR
is then pulsed low and data
transfer into the selected register occurs on the rising
edge of
WR.
DTMF GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair sent
is determined by selecting transmit DTMF (bit D4)
and the 4 DTMF bits (D0-D3) of the Tone Register.
Transmission of DTMF tones from TXA is gated by
the transmit enable bit of CR0 (bit D1) as with all
other analog signals.
Page: 4 of 34
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
PIN DESCRIPTION
POWER
NAME
GND
VDD
VREF
ISET
PIN
1
16
31
28
TYPE
I
I
O
I
DESCRIPTION
System ground
Power supply input, 5 V ±10% Bypass with 0.1 and 22 µF
capacitors to GND.
An internally generated reference voltage. Bypass with 0.1
µF capacitor to ground.
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MΩ resistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
AD0-AD7
13
5-12
I
I/O
ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on
CS.
ADDRESS/DATA BUS: These bi-directional tri-state
multiplexed lines carry information to and from the internal
registers.
CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if
CS
(latched) is not active. The state of
CS
is latched on the
falling edge of ALE.
OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt.
INT
will stay low until the processor
reads the detect register or does a full reset.
READ: A low requests a read of the 73K324BL internal
registers. Data can not be output unless both
RD
and the
latched
CS
are active or low.
RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
CS
23
I
CLK
2
O
INT
20
O
RD
15
I
RESET
30
I
Page: 5 of 34
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
PCB设计
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