Advanced v0.5
ProASIC3
®
E Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
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600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
1 kbit of FlashROM with Synchronous Interfacing
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE1532-
compliant)
FlashLock
®
to Secure FPGA Contents
1.5 V Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
®
Pro (Professional) I/O
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700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/
2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X, and LVCMOS
2.5 V/5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V/3.3 V,
GTL 2.5 V/3.3 V, HSTL Class I and II, SSTL2 Class I and II,
SSTL3 Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
IEEE1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the ProASIC3E Family
Six CCC Blocks, Each with an Integrated PLL
Flexible Phase-Shift, Multiply/Divide, and Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
True Dual-Port SRAM (except x18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory
High Performance
In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL
Low Power
SRAMs and FIFOs
High-Performance Routing Hierarchy
Soft ARM7™ Core Support in M7 ProASIC3E
Devices
•
CoreMP7Sd (with debug) and CoreMP7S (without debug)
Table 1 •
ProASIC3E Product Family
A3PE600
1
ProASIC3E Devices
ARM-Enabled ProASIC3E Devices
System Gates
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
2
VersaNet Globals
3
I/O Banks
Maximum User I/Os
Package Pins
PQFP
FBGA
A3PE1500
M7A3PE1500
1.5 M
38,400
270
60
1k
Yes
6
18
8
439
PQ208
FG484, FG676
A3PE3000
M7A3PE3000
3M
75,264
504
112
1k
Yes
6
18
8
616
PQ208
FG484, FG896
M7A3PE600
600 k
13,824
108
24
1k
Yes
6
18
8
270
PQ208
FG256, FG484
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the
ProASIC3 Flash FPGAs
datasheet.
April 2006
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
ProASIC3E Flash Family FPGAs
I/Os Per Package
1
ProASIC3E Devices
ARM-Enabled
ProASIC3E Devices
A3PE600
M7A3PE600
Single-Ended
I/O
1
147
165
270
–
–
Differential
I/O Pairs
65
79
135
–
–
A3PE1500
3
A3PE3000
3
M7A3PE3000
Single-Ended
I/O
1
147
–
280
–
616
Differential
I/O Pairs
65
–
136
–
300
M7A3PE1500
I/O Types
Single-Ended
I/O
1
147
–
280
439
–
Differential
I/O Pairs
65
–
136
209
–
Package
PQ208
FG256
FG484
FG676
FG896
Notes:
1. When considering migrating your design to lower or higher density devices, refer to the
"Package Pin Assignments" section on
page 4-1
to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per minibank
(group of I/Os). Refer to the
"I/O Banks and I/O Standards Compatibility" section on page 2-28
for more information about V
REF
and
the use of minibanks.
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A d v a n c e d v 0 .5
ProASIC3E Flash Family FPGAs
ProASIC3E Ordering Information
A3PE3000 _
1
FG
G
896
I
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to +70˚C)
I = Industrial (–40˚C to +85˚C)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant (Green) Packaging
Package Type
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F
Blank
1
2
=
=
=
=
20% Slower than Standard*
Standard
15% Faster than Standard
25% Faster than Standard
Part Number
ProASIC3E Devices
A3PE600 = 600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
ARM-Enabled ProASIC3E Devices
M7A3PE600 = 600,000 System Gates
M7A3PE1500 = 1,500,000 System Gates
M7A3PE3000 = 3,000,000 System Gates
Note:
*–F Speed Grade – DC and switching based only on simulation. The characteristics are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this document. This speed grade is only
supported in commercial temperature range.
Temperature Grade Offerings
A3PE600
Package
PQ208
FG256
FG484
FG676
FG896
M7A3PE600
C, I
C, I
C, I
–
–
A3PE1500
M7A3PE1500
C, I
–
C, I
C, I
–
A3PE3000
M7A3PE3000
C, I
–
C, I
–
C, I
Note:
C = Commercial Temperature Range: 0°C to 70°C Ambient
I = Industrial Temperature Range: –40°C to 85°C Ambient
A d v a n c ed v 0.5
iii
ProASIC3E Flash Family FPGAs
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial
temperature range.
2. C = Commercial Temperature Range: 0°C to 70°C Ambient
3. I = Industrial Temperature Range: –40°C to 85°C Ambient
–F
✓
–
1
Std.
✓
✓
–1
✓
✓
–2
✓
✓
Datasheet references made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The part numbers
start with M7.
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
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A d v a n c e d v 0 .5
ProASIC3E Flash Family FPGAs
Table of Contents
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
A d va n ce d v 0 . 5
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