November 2003
rev 1.1
3.3V Peak Reducing Zero Delay Buffer
General Features
10 MHz to 133- MHz operating range, compatible
with CPU and PCI bus frequencies.
•
•
•
EMI reduced output with on-chip EMI reduction
capability.
Zero input - output propagation delay.
Multiple low-skew outputs.
•
•
•
•
•
•
•
Output-output skew less than 250 ps.
Device-device skew less than 700 ps.
One input drives 9 outputs, grouped as 4 + 4 + 1
One input drives 5 outputs (ASM5P23SS05A).
®
ASMP5P23SS09A
ASMP5P23SS05A
typically 1000 times slower than the fundamental clock, the
spread spectrum process has negligible impact on system
performance while giving significant cost savings. Alliance
offers options with different spreading patterns with more
spread and greater EMI reduction.
The -1H version of the ASM5P23SXXA operates at up to
133- MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P23SS09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P23SS09A and ASM5P23SS05A devices
can accept the same input clock and distribute it. In this
case the skew between the outputs of the two devices is
guaranteed to be less than 700ps. All outputs have less
than 200 ps of cycle-to-cycle jitter. The input and output
propagation delay is guaranteed to be less than 250 ps,
and the output to output skew is guaranteed to be less than
250ps.
The ASM5P23SS09A and the ASM5P23SS05A are
available in two different configurations, as shown in the
ordering information table. The ASM5P23SXXA-1 is the
base part. The ASM5P23SXXA-1H is the high drive version
of the -1 and its rise and fall times are much faster than -1
part.
Peak Reducing
PLL
REF
CLKOUT
CLK1
CLK2
CLK3
CLK4
(ASM5P23SS09A).
Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium based systems.
Test Mode to bypass PLL (ASM5P23SS09A only, refer
Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP,
and 150-mil SSOP packages (ASM5P23SS09A) or in
8-pin, 150-mil SOIC package (ASM5P23SS05A).
•
3.3V operation, advanced 0.35µ CMOS technology.
Functional Description
ASM5P23SS09A is a versatile, spread spectrum output,
3.3V zero-delay buffer designed to distribute high-speed
clocks with EMI suppression capability. It is available in a
16-pin package. The ASM5P23SS05A is the eight-pin
version of the ASM5P23SS09A. It accepts one reference
input
and
drives
out
five
low-skew
clocks.
The
ASM5P23SXXA family incorporates the latest advances in
PLL spread spectrum techniques to greatly reduce the
peak EMI by modulating the output frequency with a low
frequency carrier. The ASM5P23SXXA allows significant
system cost savings by reducing the number of circuit
board layers and shielding that are traditionally required to
pass EMI regulations. Because the modulating frequency is
Block Diagram
REF
Peak Reducing
PLL
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
S2
S elect Inpu t
Decoding
CLKB1
CLKB2
CLKB3
CLKB4
S1
ASM5P23SS05A
ASM5P23SS09A
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
Select Input Decoding for ASM5P23SS09A
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
CLKOUT
1
Driven
Driven
Driven
Driven
ASMP5P23SS09A
ASMP5P23SS05A
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to
change the skew between the reference and the output.
wave
is
composed
of
fundamental
frequency
and
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay
.
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of EMI.
Regulatory
agencies
test
electronic
equipment
by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as the
frequency increases. The standard methods of reducing
EMI are to use shielding, filtering, multi- layer-PCBs etc.
These methods are expensive. Spread spectrum clocking
reduces the peak energy by reducing the Q factor of the
clock. This is done by slowly modulating the clock freqency.
The ASM5P23SXXA uses the center modulation spread
spectrum technique in which the modulated output
frequency varies above and below the reference frequency
with a specified modulation rate. With center modulation,
the average frequency is the same as the unmodulated
frequency and there is no performance degradation
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 15
November 2003
rev 1.1
Pin Configuration
REF
CLKA1
CLKA2
V
DD
ASM5P23SS09A
ASM5P23SS05A
1
2
3
4
5
6
7
8
16
15
14
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB1
CLKB2
S2
ASM5P23SS09A
13
12
11
10
9
GND
CLKB4
CLKB3
S1
REF
CLK2
CLK1
GND
1
2
3
4
8
CLKOUT
CLK4
V
D
D
ASM5P23SS05A
7
6
5
CLK3
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 15
November 2003
rev 1.1
Pin Description for ASM5P23SS09A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
2
CLKA1
V
DD
GND
CLKB1
3
CLKB2
3
S2
4
S1
4
CLKB3
3
CLKB4
3
GND
V
DD
CLKA3
3
CLKA4
3
CLKOUT
3
3
ASM5P23SS09A
ASM5P23SS05A
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
CLKA2
3
Pin Description for ASM5P23SS05A
Pin #
1
2
3
4
5
6
7
8
Pin Name
REF
2
CLK2
3
CLK1
3
GND
CLK3
3
V
DD
CLK4
3
CLKOUT
3
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 15
November 2003
rev 1.1
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
2000
ASM5P23SS09A
ASM5P23SS05A
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P23SS05A and ASM5P23SS09A - Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
°C
pF
pF
pF
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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