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BU-65566
MIL-STD-1553 66MHz PMC Card
FEATURES
•
32-Bit/66 MHz PMC Card
•
Operates in 3.3V or 5V PCI Signaling
Environments
•
One to Four Dual Redundant MIL-STD-
1553 Channels
•
Conduction Cooled with Primary and
Secondary Thermal Interfaces
•
Shock and Vibration Tested
•
BU-65566GX Version:
Only 5V Supply Required, All Other
Supplies Generated Locally
•
BU-65566MX Version:
Both 5V and 3.3V Supplies Required
DESCRIPTION
The BU-65566 is a single- or multi-channel MIL-STD-1553 PMC card.
The design of the BU-65566 leverages DDC's industry proven
Enhanced Mini-ACE. Each channel may be independently pro-
grammed for Bus Controller (BC), Remote Terminal (RT), Monitor
(MT), or Remote Terminal/Monitor (RT/MT) operation.
Advanced architectural features of the Enhanced Mini-ACE include a
highly autonomous bus controller, an RT providing a wide variety of
buffering options, and a selective message monitor. Each Enhanced
Mini-ACE channel incorporates 64K words of RAM, and utilizes 3.3-
volt logic locally generated on the card to reduce power consumption
(BU-65566GX only). Both 5V and 3.3V supplies are required with the
BU-65566MX version.
This card includes primary and secondary thermal interfaces as per
the VITA-20-2001 specification. Cards have been subjected to multi-
axes shock & vibration testing.
•
Enhanced Mini-ACE BC, RT, MT, RT/MT
Architecture
•
Transformer-Coupled 1553 Channels
(Consult Factory for Direct Coupling)
•
64K-word RAM per Channel
•
1MB Flash Memory
•
Highly Autonomous Bus Controller
Architecture
- Message Scheduling
- Bulk Data Transfers
- Asynchronous Messages
- Retries and Bus Switching
- Data Block Double Buffering
•
RT Buffering Options
- Single Buffering
- Double Buffering
- Subaddress Circular Buffering
- Global Circular Buffering
•
Selective Message Monitor
•
Supports PCI Interrupts
•
Software Support for VxWorks®, Linux,
Integrity® and Windows® 9x/2000/XP
,
Windows NT®
FOR MORE INFORMATION CONTACT:
SOFTWARE
The BU-65566 comes bundled with a C language based Applications
Programmers Interface (API) Library and the appropriate device dri-
vers to support all modes of operation in Windows 9x/2000/XP,
Windows NT, Linux, VxWorks and Integrity. The library is comprised
of a collection of C function calls that serves to offload a great deal of
low-level tasks from the application programmer. This software sup-
ports all of the Enhanced Mini-ACE's advanced architectural features.
Optional graphical user software is available for data bus monitoring,
analysis, and simulation.
Technical Support:
1-800-DDC-5757 ext. 7771
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
© 2001 Data Device Corporation
All Trademarks used herein are the property of their respective owners.
Data Device Corporation
www.ddc-web.com
PMC
P
n
4
Connector
AD31-AD0
PCI Address/Data,
Parity, and
Bus Command/Byte
Enable
PAR
C/BE[3]# - C/BE[0]#
66 MHz,
32-Bit
PCI Target
Interface
BU-61864
Enhanced
Mini-ACE
1553
BUS A
RTAD4-0, RTADP, EXT_TRIG/SSFLAG
FRAME#, IRDY#,
IDSEL, RST#
BU-61864
Enhanced
Mini-ACE
A15-A0
D15-D0
Control
BU-61864
Enhanced
Mini-ACE
1553
BUS B
RTAD4-0, RTADP, EXT_TRIG/SSFLAG
PCI Bus
PCI Control
2
BU-65566
F-04/06-0
TRDY#, STOP#,
DEVSEL#, PERR#, SERR#
1553
BUS C
RTAD4-0, RTADP, EXT_TRIG/SSFLAG
PCI Clock
CLK
PCI Interrupt
Request
INTA#
PCI
Configuration
Registers
BU-61864
Enhanced
Mini-ACE
1553
BUS D
RTAD4-0, RTADP, EXT_TRIG/SSFLAG
FIGURE 1. BU-65566 BLOCK DIAGRAM
TABLE 1. BU-65566 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 9)
+5V
+3.3V (BU-65566MX only)
RECEIVER
Input Impedance, Transformer
Coupled (Notes 1-3)
Threshold Voltage, Transformer
Coupled
Common Mode Voltage (Note 4)
TRANSMITTER
Differential Output Voltage
Transformer Coupled Across 70
ohms
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
POWER SUPPLY REQUIREMENTS
Voltage/Tolerances
+5V
+3.3V (BU-65566MX only)
Current Drain
BU-65566X1
+5V
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3V (BU-65566M1 only)
BU-65566X2
+5V
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3V (BU-65566M2 only)
BU-65566X3
+5V
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3V (BU-65566M3 only)
BU-65566X4
+5V
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3V (BU-65566M4 only)
POWER DISSIPATION (NOTE 9)
BU-65566X1
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-65566X2
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-65566X3
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
BU-65566X4
• Idle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next
Message (Non-enhanced BC
Mode)
MIN
TYP
MAX
UNITS
TABLE 1. BU-65566 SPECIFICATIONS (CONT.)
PARAMETER
1553 MESSAGE TIMING (CONT)
BC Intermessage Gap - (Note 5)
Non-Enhanced BC mode (Mini-ACE
compatible)
Enhanced BC mode (Note 6)
BC/RT/MT Response Timeout (Note 7)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time (mid-parity to
mid-sync) (Note 8)
Transmitter Watchdog Timeout
THERMAL
Operating Temperature at Thermal Rail
BU-65566MX-900
BU-65566GX-200
BU-65566GX-300
Thermal Resistance
Junction to Thermal Interface “M”
Storage Temperature “M”
“G”
MECHANICAL DESIGN
Shock: Three pulses, half sine on six
(6) axes
Vibration: Random input, one hour
each axes 40g’s 11 msec/axes, three
hours total, 15 to 2000 Hz
Resonant Frequency: BU-65566X2
(calculated) 12Hz
PHYSICAL CHARACTERISTICS
Size
Weight
BU-65566X1
BU-65566X2
BU-65566X3
BU-65566X4
MIN
TYP
MAX
UNITS
-0.3
-0.3
1.000
0.200
6.0
4.6
V
V
Kohm
9.5
10.1
17.5 18.5
21.5 22.5
49.5 50.5
127 129.5
4
660.5
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
µs
µs
0.860
10
Vp-p
Vpeak
18
-250
100
20
150
150
27
250
300
Vp-p
mVpeak
ns
-55
-40
0
-65
-65
+85
+85
+55
+39
+160
+105
°C
°C
°C
°C/W
°C
°C
4.75
3.0
5.0
3.3
5.5
3.6
V
V
40g’s, 11 msec/axes
14g’s rms
12 Hz
250
470
635
280
521
705
80
mA
mA
mA
mA
mA
mA
A
mA
mA
A
A
mA
mA
A
A
mA
355
394
855
770
1.091 1.211
120
505
455
1.076 1.195
1.629 1.808
160
550
611
1.375 1.526
2.192 2.433
200
5.659 x 2.913
(144 x 74)
2.7 (76.5)
3.3 (93.56)
3.9 (110.6)
4.5 (127.6)
in.
(mm)
oz. (g)
oz. (g)
oz. (g)
oz. (g)
1.3
1.6
1.8
1.8
2.4
2.7
2.3
3.3
3.9
2.8
4.1
5.4
2.5
1.4
1.9
2.1
2.0
2.9
3.3
2.5
3.9
4.8
3.1
4.8
6.6
W
W
W
W
W
W
W
W
W
W
W
W
µs
TABLE 1 notes:
(Notes 1 through 3 are applicable to the Input Impedance specification:)
(1) The specifications are applicable for both unpowered and powered conditions.
(2) The specifications assume a 2 Volt rms balanced, differential, sinusoidal input.
The applicable frequency is 75 kHz to 1 MHz.
(3) Minimum impedance is guaranteed over the operating range, but is not tested.
(4) Assumes a common mode voltage within the frequency range of dc to 2MHz,
applied to pins of the isolation transformer on the stub side (transformer cou-
pled), and referenced to signal.
(5) Typical value for minimum intermessage gap time. Under software control, this
may be lengthened to 65,535 ms. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic “1”, then host accesses during BC Start-
of-Message (SOM) and End-of-Message (EOM) transfer sequences could have
the effect of lengthening the intermessage gap time. For each host access during
an SOM or EOM sequence, the intermessage gap time will be lengthened by 6
clock cycles. Since there are 7 internal transfers during SOM, and 5 during EOM,
this could theoretically lengthen the intermessage gap by up to 72 clock cycles;
i.e., 4.5 µs.
(6) For enhanced BC mode, the typical value for intermessage gap time is approx-
imately 625 ns longer than for the non-enhanced BC mode.
(7) Software programmable (4 options). Includes RT-to-RT Timeout (measured mid
parity of transmit Command Word to mid-sync of Transmitting RT Status Word).
(8) Measured from mid-parity crossing of Command Word to mid-sync crossing of
RT’s Status Word.
(9) Power dissipation specifications assume a transformer coupled configuration
with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
(10) All power measurements are for a 33 MHz PCI bus.
Data Device Corporation
www.ddc-web.com
3
BU-65566
F-04/06-0
INTRODUCTION
The BU-65566 is a single- or multi-channel MIL-STD-1553
66MHz PMC card built in accordance with IEEE PMC Physical
and Environmental Layers Standard. The BU-65566 is available
with one to four dual redundant 1553 channels on a conduction-
cooled card with an operating temperature of -55° to +85°C,
-40° to +85°C, or 0° to +55°C measured at the rail.
The design of the BU-65566 leverages the field proven
Enhanced Mini-ACE. Each channel may be independently pro-
grammed for BC, RT, Monitor, or RT/Monitor mode.
bility over current sources. This serves to improve performance on
long buses with many taps. The BU-65566's transmitters may be
trimmed to meet the MIL-STD-1760 requirement of a minimum of
20 volts peak-to-peak, transformer coupled (consult factory).
If required, the BU-65566 is also available with an option for
McAir compatible transmitters (consult factory).
FLASH MEMORY
The BU-65566 PMC card includes an 8Mbit (1MB) flash memo-
ry. The flash memory is available to a user (via PCI mapping) for
non-volatile storage. The memory may also be used to store
Enhanced Mini-ACE configuration data. This configuration data
is then used to auto-initialize any or all of the Enhanced Mini-
ACE channels at power-on.
ENHANCED MINI-ACE
The BU-65566 PMC card incorporates a PCI bridge, along with
between one and four of DDC's Enhanced Mini-ACE hybrid(s).
Each Enhanced Mini-ACE comprises a complete, independent
interface between the PCI bridge and a MIL-STD-1553 bus. The
Enhanced Mini-ACE hybrids provide software compatibility with
DDC's older generation ACE and Mini-ACE (Plus) terminals.
The card provides complete multiprotocol support of MIL-STD-
1553A/B and STANAG 3838. These hybrids include dual trans-
ceivers, along with protocol, host interface, memory manage-
ment logic, and 64K X 16 of RAM with built-in parity checking.
One of the features of the Enhanced Mini-ACE is its enhanced Bus
Controller (BC) architecture. The Enhanced BC's autonomous
message sequence control engine provides a means for offloading
the host processor for implementing multi-frame message sched-
uling, message retry and bus switching schemes, data double
buffering, and asynchronous message insertion. In addition, the
Enhanced BC mode includes 8 general purpose flag bits, a gener-
al purpose queue, and user-defined interrupts, for the purpose of
performing messaging to the host processor. This all serves to
greatly reduce the amount of host processing bandwidth required.
Another important feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test.
The Enhanced Mini-ACE Remote Terminal (RT) offers the choice
of single, double, and circular buffering for individual subad-
dresses along with a global circular buffering option for multiple
(or all) receive subaddresses, a 50% rollover interrupt for circu-
lar buffers, and an interrupt status queue for logging up to 32
interrupt events. The RT can be configured, via API library to reli-
ably transfer data from RT hardware to a host buffer when one of
these interrupts occurs. The library also allows for the creation of
a user defined Interrupt Service Routine (ISR) on any of the
available interrupts of the Enhanced Mini-ACE.
The transceivers in the Enhanced Mini-ACE series terminals are
fully monolithic, requiring only a +5 volt power input. The transmit-
ters are voltage sources, which provide improved line driving capa-
Data Device Corporation
www.ddc-web.com
4
BUILT-IN SELF-TEST
The Enhanced Mini-ACE includes extensive, highly autonomous
self-test capability. This includes both protocol and RAM self-tests.
The Enhanced Mini-ACE protocol test is performed automatically
following power turn-on. In addition, either or both of these self-tests
may be initiated by command(s) from the BU-65566's PCI host. The
API library includes functions to easily perform these tests.
THERMAL DESIGN
The thermal design of this card includes thermal vias located
under the Enhanced Mini-ACE transceiver chips. The transceiver
chips have the highest heat dissipation on the card: 1.22 watts
maximum at 100% transmit duty cycle. Thermally conductive
epoxy in the form of a paste adhesive is applied to the PC board
in the areas under the Enhanced Mini-ACE devices in the Military
(M) version of this card. Heat is conducted through the thermal
vias to an inner copper plane layer, which functions as a heat
spreader. The heat path includes additional thermal vias from the
thermal plane layer to the two copper strips which run the width
of the card (primary thermal interface) and the two copper strips
which run part of the length of the card (secondary thermal inter-
face). Thermal rails from the card base may then be bolted to the
copper strips, providing a path for removing heat from the card.
The BU-65566 “M” card's total thermal resistance, from trans-
ceiver chip junction to the copper strip/thermal rail interface, is 39°
C/W max. This includes the T
JC
of 11° C/W max for the Enhanced
Mini-ACE hybrid and a thermal resistance of 28°C/W max for the
card, i.e., from the hybrid case to the copper strip/thermal rail
interface. With a rail temperature of 85°C, this results in a maxi-
mum junction temperature of 129°C at 100% transmit duty cycle.
Since the transmit duty cycle for most 1553 BC’s and RT’s is sig-
nificantly less than 100%, this provides ample headroom below
the transceiver chip's maximum junction temperature of 160°C.
BU-65566
F-04/06-0
For the BU-65566GX-200 card, the rail temperature can range
from -40°C to +85°C. DDC has designed this board to operate
under these temperature conditions.
ACE(s) are logically Or'ed together to provide a single interrupt
for the card.
REGISTER AND MEMORY ADDRESSING
MECHANICAL DESIGN
Test specimens of the BU-65566 card were subjected to Shock
and Random Vibration testing. All devices were non-operational
during all phases of testing and exhibited no evidence of physi-
cal damage at the conclusion of testing.
Three (3) shock pulses were applied in each of the following six
(6) test directions: Horizontal (+X), Horizontal (+Z), Vertical (+Y),
Horizontal (-X), Horizontal (-Z), and Vertical (-Y). Each applied
shock pulse was Half-Sine in wave shape, at an input amplitude
of 40 g's and a duration of 11 milliseconds.
Random vibration was independently applied for one (1) hour to
each of three (3) orthogonal axes resulting in a total test time of
three (3) hours. Testing was performed with the input applied
along the Horizontal (X), Horizontal (Z) and Vertical (Y) test axes.
Test specimens were subjected to a Random input, in the fre-
quency range of 15 to 2000 Hz at .1g
2
/ Hz.
PMC cards are optionally conformally coated with Humiseal
1A33 polyurethane coating. Please see the ordering information
in the back of this data sheet for details.
The BU-65566 PCI interface contains a set of "Type 00h" PCI
configuration registers that are used to map the device into the
host system. The PCI configuration register space is mapped in
accordance with PCI revision 2.2 specifications. These registers
are arranged such that all Enhanced Mini-ACE memory and reg-
ister space may be addressed through a single PCI function.
The PCI configuration space of this card is described in the BU-
65565/66 Card Manual. When using this card with one of DDC's
drivers and the Enhanced Mini-ACE API library software, the
details of these registers and memory addresses are abstracted
from the user.
ENHANCED MINI-ACE REGISTER AND
MEMORY ADDRESSING
The software interface between each Enhanced Mini-ACE and
the PCI host consists of 24 internal operational registers for nor-
mal operation, an additional space for 40 test mode registers,
and 64K words of shared memory address space.
Enhanced Mini-ACE registers may only be accessed as 16-bit
words. If a 32-bit read access is attempted, the upper 16 bits will
not be valid. That is, register accesses are on a 32-bit boundary
(e.g., 000 = Enhanced Mini-ACE Register 0, 004 = Enhanced
Mini-ACE Register 1, 008 = Enhanced Mini-ACE Register 2,
etc). For normal operation, the host processor only needs to
access the lower 32 register address locations (00-1F). The next
32 locations (20-3F) should be reserved, since many of these
are used for factory test.
Enhanced Mini-ACE memory may be accessed as either single
16-bit words, or as a 32-bit double word. For the latter, a packed
pair of 16-bit words at adjacent memory address locations will be
accessed.
Note that the addressing for all Enhanced Mini-ACE pointers is
word-oriented, while all PCI addressing is byte-oriented. That is,
the value of a pointer stored in Enhanced Mini-ACE RAM will be
half of the value of the PCI address offset from the base memory
address for the particular Enhanced Mini-ACE. If not using the
Enhanced Mini-ACE API Library and you would like more informa-
tion about the Enhanced Mini-ACE registers and memory address-
es please reference the Enhanced Mini-ACE User’s Guide.
When using the API library provided with your card, the
Enhanced Mini-ACE registers and memory accesses are
abstracted from the end user to provide an easy-to-use High
Level C programming environment.
PCI INTERFACE
As a means of minimizing power consumption and dissipation,
the design of the standard BU-65566 card utilizes +3.3 volt
power for the PCI interface and 1553 (Enhanced Mini-ACE)
logic. The 1553 transceivers and RAM are powered by +5 volts.
The default configuration of the BU-65566GX card provides an
on board voltage regulator for applications where +3.3 volt power
is not available. On the other hand, the BU-65566MX requires
that both +5.0V and +3.3V be available on the PMC connector.
DDC is able to supply a non-standard version of the BU-65566GX card
where the voltage regulator is removed and the card will utilize the +3.3V
power supply pins on the PMC connector (consult factory).
The BU-65566's PCI interface is a fully compliant target (slave)
agent, as defined by the PCI Local Bus Specification Revision
2.2, using a 32-bit interface that operates at clock speeds of up
to 66 MHz, in a +3.3 volt or +5 volt signaling environment. The
interface supports PCI interrupts and contains a 72 X 32 FIFO to
accelerate burst write transfers from the PCI host.
INTERRUPTS
The Enhanced Mini-ACE's may issue interrupt requests over the
PCI bus. PCI interrupts are generated on the INTA# output sig-
nal to the PCI host. The interrupts from each Enhanced Mini-
Data Device Corporation
www.ddc-web.com
5
BU-65566
F-04/06-0
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