CDP68HC68W1
March 1998
CMOS Serial Digital Pulse Width Modulator
Description
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
V
T
pin rises above 0.75V. The CDP68HC68W1 is supplied in
an 8 lead PDIP package (E suffix).
Features
• Programmable Frequency and Duty Cycle Output
• Serial Bus Input; Compatible with Motorola/Intersil
SPI Bus, Simple Shift-Register Type Interface
• 8 Lead PDIP Package
• Schmitt Trigger Clock Input
• 4V to 6V Operation, -40
o
C to 85
o
C Temperature Range
• 8MHz Clock Input Frequency
Pinout
CDP68HC68W1
(PDIP)
TOP VIEW
CLK
CS
V
T
V
SS
1
2
3
4
8
7
6
5
V
DD
PWM
SCK
DATA
Ordering Information
PART NUMBER
CDP68HC68W1E
TEMP. RANGE
(
o
C)
-40 to 85
PACKAGE
8 Ld PDIP
PKG.
NO.
E8.3
Block Diagram
CLK
INPUT CLK
MODULATOR
LOGIC
PWM
8 - STAGE RIPPLE
COUNTER
8 - STAGE RIPPLE
COUNTER
RESET
PULSE - WIDTH
DATA REGISTER
LOAD
FREQUENCY
DATA REGISTER
LOAD
DATA
8 - STAGE SHIFT
REGISTER
8 - STAGE SHIFT
REGISTER
CONTROL REGISTER
2 - STAGE SHIFT
LOAD
V
T
V
T
COMPARATOR
SCK
8
16
24
5 - STAGE 24 - STATE
COMPARATOR
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
1919.3
1
CDP68HC68W1
Absolute Maximum Ratings
DC Supply Voltage Range, (V
DD
) . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to V
SS
Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input.
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . 100mW
Maximum Storage Temperature Range (T
STG
) . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 265
o
C
At Distance 1/16
±1/32
in. (1.59
±
0.79mm)
From Case for 10s Max
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
T
A
= Full Package Temperature Range (All Package Types)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CDP68HC68W1,
V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= -40
o
C to 85
o
C
DC Operating Voltage Range
Input Voltage Range (Except V
T
Pin)
-
V
IH
V
IL
V
T
Pin Output Voltage Threshold
Device Current in “Power Down” Mode, Clock Disabled
Low Level Output Voltage (I
OL
= 1.6mA)
High Level Output Voltage (I
OH
= -1.6mA)
Input Leakage Current
Operating Device Current (f
CLK
= 1MHz)
Clock Input Capacitance
(V
IN
= 0V, f
CLK
= 1MHz, T
A
= 25
o
C)
V
IT
I
PD
V
OL
V
OH
I
IN
I
OPER
C
IN
4
0.7•V
DD
-0.3
0.4
-
-
V
DD
- 0.4V
-
-
-
-
-
-
-
-
-
-
-
-
-
6
V
DD
+0.3V
0.3•V
DD
0.15•V
DD
1
0.4
-
±1
1
10
V
V
V
V
µA
V
V
µA
mA
pF
Control Timing
PARAMETER
CDP68HC68W1,
V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= -40
o
C to 85
o
C
Clock Frequency
Cycle Time
Clock to PWM Out
Clock High Time
Clock Low Time
Rise Time (20% V
DD
to 70% V
DD
)
Fall Time (70% V
DD
to 20% V
DD
)
F
CLK
t
CYC
t
PWMO
t
CLKH
t
CLKL
t
R
t
F
DC
-
-
50
50
-
-
8.0
-
125
-
-
100
100
MHz
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
MAX
UNITS
2
CDP68HC68W1
Introduction
The digital pulse width modular (DPWM) divides down a
clock signal supplied via the CLK input as specified by the
control, frequency, and pulse width data registers. The
resultant output signal, with altered frequency and duty
cycle, appears at the output of the device on the PWM pin.
Functional Description
Serial Port
Data are entered into the three DPWM registers serially
through the DATA pin, accompanied by a clock signal applied
to the SCK. The user can supply these serial data via shift
register(s) or a microcontroller’s serial port, such as the SPI
port available on most CDP68HC05 microcontrollers. Micro-
controller I/O lines can also be used to simulate a serial port.
Data are written serially, most significant bit first, in 8, 16 or
24-bit increments. Data are sampled and shifted into the
PWMs shift register on each rising edge of the SCK. The
serial clock should remain low when inactive. Therefore,
when using a 68HC05 microcontroller’s SPI port to provide
data, program the microcontroller’s SPI control register bits
CPOL, CPHA to 0, 0.
The CDP68HC68W1 latches data words after device
deselection. Therefore, CS must go high (inactive) following
each write to the W1.
Power-Up Initialization
Upon V
DD
power up, the output of the PWM chip will remain
at a low level (logic zero) until:
1. The chip is selected (CS pin pulled low).
2. 24-bit of information are shifted in.
3. The chip is deselected (CS pin pulled high).
The 24-bits of necessary information pertain to the loading
of the PWM 8-bit registers, in the following order:
1. Control register
2. Frequency register
3. Pulse width register
See section entitled
Pulse Width Modulator Data Regis-
ters
for a description of each register. Once initialized, the
specified PWM output signal will appear until the device is
reprogrammed or the voltage on the V
T
pin rises above the
specified threshold. Reprogramming the device will update
the PWM output after the end of the present output clock
period.
Reprogramming Shortcuts
After the device has been fully programmed upon power up,
it is only necessary to input 8 bits of information to alter the
output pulse width, or 16 bits to alter the output frequency.
Altering the Pulse Width:
The pulse width may be
changed by selecting the chip, inputting 8 bits, and dese-
lecting the chip. By deselecting the chip, data from the first
8-bit shift register are latched into the pulse width register
(PWM register). The frequency and control registers
remain unchanged. The updated PWM information will
appear at the output only after the end of the previous total
output period.
Altering the Frequency:
The frequency can be changed by
selecting the chip, inputting 16 bits (frequency information
followed by pulse width information), and deselected the
Functional Pin Description
V
DD
and V
SS
These pins are used to supply power and establish logic lev-
els within the PWM. V
DD
is a positive voltage with respect to
V
SS
(ground).
CLK
The CLK pin is an input only pin where the clock signal to be
altered by the PWM circuitry is supplied. This is the source
of the PWM output. This input frequency can be internally
divided by either one or two, depending on the state of the
CD bit in the control register.
CS
The CS pin is the chip select input to the PWM’s SPI inter-
face. A high-to-low (1 to 0) transition selects the chip. A low-
to-high (0 to 1) transition deselects the chip and transfers
data from the shift registers to the data registers.
VT
The VT pin is the input to the voltage threshold comparator
on the PWM. An analog voltage greater than 0.75V (at V
DD
= 5V) on this pin will immediately cause the PWM output to
go to logic “0”. This will be the status until the V
T
input is
returned to a voltage below 0.4V, the W1 is deselected, and
then one or more of the data registers is written to.
An analog voltage on this pin less than 0.75V (at V
DD
= 5V)
will allow the device to operate as specified by the values in
the registers.
DATA
Data input at this pin is clocked into the shift register (i.e.,
latched) on the rising edge of the serial clock (SCK), most
significant bits first.
SCK
The SCK pin is the serial clock input to the PWM’s SPI inter-
face. A rising edge on this pin will shift data available at the
(DATA) pin into the shift register.
PWM
This pin provides the resultant output frequency and pulse
width. After V
DD
power up, the output on this pin will remain
a logic “0”, until the chip is selected, 24 bits of information
clocked in, and the chip deselected.
5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
