MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145421/D
ISDN Universal Digital Loop
Transceivers II
(UDLT II)
MC145421
MC145425
Freescale Semiconductor, Inc...
The MC145421 and MC145425 UDLTs are high–speed data transceivers
capable of providing 160 kbps full–duplex data communication over 26 AWG
P SUFFIX
.
PLASTIC PACKAGE
24
and larger twisted–pair cable up to 1 km in length. These devices are primarily
C
1
CASE 709
used in digital subscriber voice and data telephone systems. In addition, the
IN
,
devices meet and exceed the CCITT recommendations for data transfer rates
OR
of ISDNs on a single twisted pair. The devices utilize a 512 kbaud MDPSK burst
CT
modulation technique to supply the 160 kbps full–duplex data transfer rates.
DW SUFFIX
DU
The 160 kbps rate is provided through four channels. There are two B channels,
N
SOG PACKAGE
24
which are 64 kbps each. In addition, there are two D channels which are
CASE 751F
CO
1
I
16 kbps each.
The MC145421 and MC145425 UDLTs are designed for upward compatibility
EM
ORDERING INFORMATION
with the existing MC145422 and MC145426 80 kbps UDLTs, as well
S
compa–
E
as
tibility with existing and evolving telephone switching hardware and software
MC145421P
Plastic Package
AL
C
MC145425P
Plastic Package
architectures.
S
the telephone switch
The MC145421 (Master) UDLT is designed for use at
MC145421DW SOG Package
EE
for use at the remote
line card while the MC145425 (Slave) UDLT is designed
R
MC145425DW SOG Package
F
digital telset or data terminal.
Y
•
Employs CMOS Technology in Order to Take Advantage of Its Proven
ED
LSI Functions
Capability for Complex Analog
V
Digital
I
and
•
Provides Synchronous Full–Duplex 160 kbps Voice and Data
CH
Communication in a 2B+2D Format for ISDN Compatibility
R
•
Provides the CCITT
A
Basic Access Data Transfer Rate (2B+D) for ISDNs
on a Single Twisted Pair Up to 1 km
•
Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signaling Schemes
•
Protocol Independent
•
Single + 5 V Power Supply
•
MC145421EVK is Available
B
16 kbps D1
16 kbps D2
64 kbps B1
64 kbps B2
TWISTED PAIR
WIRE
≤
1 km
MASTER
ISDN UDLT
160 kbps FULL–DUPLEX
DATA TRANSMISSION
SLAVE
ISDN UDLT
16 kbps D1
16 kbps D2
64 kbps B1
64 kbps B2
REV 2 (Replaces ADI1251)
9/95
©
Motorola, Inc. 1995
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
MC145421•MC145425
1
Freescale Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS
(Voltage Referenced to VSS)
Rating
DC Supply Voltage
Voltage Any Pin to VSS
DC Current, Any Pin (Excluding VDD,
VSS)
Operating Temperature
Storage Temperature
Symbol
VDD – VSS
V
I
TA
Tstg
Value
– 0.5 to 6.5
– 0.5 to VDD + 0.5
±
10
– 40 to + 85
– 85 to + 150
Unit
V
V
mA
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high imped-
ance circuit. For proper operation it is recom-
mended that Vin and Vout be constrained to
the range VSS
≤
(Vin or Vout)
≤
VDD. Reliability
of operation is enhanced if unused inputs are
tied to an appropriate logic voltage level (e.g.,
either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS
(TA = – 40 to + 85°C)
Parameter
DC Supply Voltage
Frame Rate MC145421 (See Note)
MC145421/25 Frame Slip Rate (See Note)
Pins
VDD
MSI
—
Freescale Semiconductor, Inc...
CCI Clock Frequency
TDC/RDC Data Clocks (for Master)
DCLK
Modulation Baud Rate (CCI/16)
LE
NOTE: The slave’s crystal frequency divided by 1024 must equal the master’s MSI frequency
±
0.25% for optimum operation. Also, the
CA
8.192 MHz input at the master divided by 1024 must be within 0.048% of the master’s 8 kHz MSI clock frequency.
ES
E
DIGITAL CHARACTERISTICS
(VDD = 5 V, TA = –
R
to + 85°C)
40
F
Y
Min
Max
Unit
Parameter
B
Input High Level
3.5
—
V
ED
Input Low Level
—
1.5
V
IV
H
Input Current, VDD
—
15
mA
RC
A
Input Current (Digital Pins)
—
5
µA
—
512
—
kHz
Input Capacitance
Output High Current (Except Tx on Master and Slave, and PD on the Slave)
Tx Output High Current
PD (Slave) Output High Current (See Note)
Output Low Current (Except Tx on Master and Slave, and PD on Slave)
Tx Output Low Current
PD (Slave) Output Low Current (See Note)
Tx Three–State Impedance
XTL Output High Current
XTL Output Low Current
VOH = 4.6
VOH = 2.5
VOH = 4.6
VOH = 2.5
VOH = 4.6
VOH = 2.5
VOL = 0.4
VOL = 0.8
VOL = 0.4
VOL = 0.8
VOL = 0.4
—
– 1.7
– 0.36
– 3.4
– 0.7
—
0.36
0.8
1.7
3.5
30
100
—
10
—
—
—
—
– 90
—
—
—
—
60
—
– 450
pF
mA
mA
µA
mA
mA
µA
kΩ
µA
µA
S
LO2
LO1,
O
—
C
I
M
—
E
—
,I
—
OR
8.0
T
—
C
—
U
8.192
ND
—
4.5
5.0
0.128
0.016
—
—
Min
Typ
C.
N
Max
5.5
—
0.25
8.29
4.1
4.1
Unit
V
kHz
%
MHz
MHz
MHz
VOH = 0.4
450
—
NOTE: To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of
±
800
µA
drive capability.
ANALOG CHARACTERISTICS
(VDD = 5 V, TA = 0 to 70°C)
Parameter
Modulation Differential Amplitude RL = 880
Ω
(LO1 – LO2)
Modulation Differential DC Offset
Vref Voltage (Typically 9/20
S
(VDD – VSS))
PCM Tone Level
Demodulator Input Amplitude
Demodulator Input Impedance (LI to Vref)
Min
4.6
—
2.0
– 22
50
75
Max
—
40
2.5
– 18
—
300
Unit
Vpeak
mV
V
dBm
mVpeak
kΩ
MC145421•MC145425
4
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
MC145421 MASTER PIN DESCRIPTIONS
VDD
Positive Supply (Pin 24)
The most positive power supply pin, normally + 5 V with
respect to VSS.
VSS
Negative Supply (Pin 1)
The most negative supply pin and logic ground, normally
0 V.
Vref
Reference Output (Analog Ground) (Pin 2)
This pin is the output of the internal reference supply and
should be bypassed to VDD and VSS with 0.1
µF
capacitors.
This pin usually serves as an analog ground reference for
transformer coupling of the device’s incoming bursts from the
line. No external dc load should be placed on this pin.
transmitting every MSI period to the slave device, shortly
after the rising edge of MSI. The state of this pin is latched if
the SE pin is held low.
VD
Valid Data Output (Pin 5)
A high level on this pin indicates that a valid line transmis-
sion has been demodulated. A valid transmission burst is
determined by proper synchronization and the absence of
detected bit errors. VD changes state on the rising edge of
MSI when PD is high. When PD is low, VD changes state at
the end of demodulation of a transmission burst and does not
change again until three MSI rising edges have occurred, at
which time it goes low, or until the next demodulation of a
C.
output and is high
burst. VD is a standard B–series CMOS
N
,I
impedance when SE is low.
R
MSI
UC
Master Sync Input (Pin 16)
D
TO
Freescale Semiconductor, Inc...
This pin
O
the master, 8 kHz frame reference input. The
is
C
of MSI loads B and D channel data which had
LI
I
rising edge
M
during the previous frame into the modulator sec-
Line Input (Pin 3)
been input
SE
tion of the device and initiates the outbound burst onto the
This pin is an input to the demodulator for the incoming
E
bursts. The input has an internal 240 k
Ω
resistor tied to the
L
twisted–pair cable. The rising edge of MSI also initiates the
A
buffering of the B and D channel data demodulated during
Vref pin, so an external capacitor or line transformer may
C
be
S
the previous frame. MSI should be approximately leading
used to couple the input signal to the device with no dc
E
offset.
E
edge aligned with the TDC/RDC data clock input pin.
FR
LO1, LO2
CCI
BY
Line Driver Outputs (Pins 23, 22)
D
High–Speed Clock Input (Pin 17)
These push–pull outputs drive the twisted pair transmis-
E
sion line with a 512 kHz modified
I
(MDPSK) burst each
H
DPSKWhen not modulating
125
µs,
in other words at an
C
R
8 kHz rate.
the line, these pins are driven to the active high state —
A
being the same potential, they create an ac short. When
used in conjunction with feed resistors, proper line termina-
tion is maintained.
SE
Signal Enable Input (Pin 11)
At the time of a negative transition on this pin, an internal
latch stores the states of LB and PD for as long as SE is held
low. During this time, the VD, DO1, and DO2 outputs are
driven to the high–impedance state. When SE is high, all
pins function normally.
LB
Loopback Control (Pin 4)
A low level on this pin ties the internal modulator output to
the internal demodulator input, which loops the entire burst
for testing purposes. During the loopback operation, the LI
input is ignored and the LO1 and LO2 drivers are driven to
the active high level. The state of this pin is internally latched
if the SE pin is held low. This feature is only active when the
PD input is high.
PD
Power–Down Input (Pin 12)
When held low the ISDN UDLT powers down, except the
circuitry that is necessary to demodulate an incoming burst
and to output VD, B, and D channel data bits. When PD is
brought high, the ISDN UDLT powers up. Then, it begins
N
V
An 8.192 MHz clock should be supplied to this input. The
8.192 MHz input should be 50% duty cycle. However, it may
free–run with respect to all other clocks without performance
degradation.
D1I, D2I
D Channel Signaling Bit Inputs (Pins 6, 7)
These inputs are 16 kbps serial data inputs. Two bits
should be clocked into each of these inputs between the ris-
ing edges of the MSI frame reference clock. The first bit of
each D channel is clocked into an intermediate buffer on the
first falling edge of the DCLK following the rising edge of MSI.
The second bit of each D channel is clocked in on the next
negative transition of the DCLK. If further DCLK negative
edges occur, new information is serially clocked into the buff-
er replacing the previous data one bit at a time. Buffered
D channel data bits are burst to the slave device on the next
rising edge of the MSI frame reference clock.
D1O, D2O
D Channel Signal Outputs (Pins 9, 10)
These serial outputs provide the 16 kbps D channel signal-
ing information from the incoming burst. Two data bits should
be clocked out of each of these outputs between the rising
edges of the MSI frame reference clock. The rising edge of
MSI produces the first bit of each D channel on its respective
pin. Circuitry then searches for a negative D channel clock
edge. This tells the D channel data shift register to produce
the second D channel bit on the next rising edge of the
DCLK. Further positive edges of the DCLK recirculate the
D channel output buffer information.
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
MC145421•MC145425
5
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