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SY100E160JZ: 产品描述Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28; 产品类别逻辑逻辑; 文件大小59KB，共5页; 制造商Micrel ( Microchip ); 官网地址https://www.microchip.com

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SY100E160JZ概述

Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28

SY100E160JZ规格参数

参数名称	属性值
厂商名称	Micrel ( Microchip )
零件包装代码	QLCC
包装说明	QCCJ,
针数	28
Reach Compliance Code	unknown
系列	100E
JESD-30 代码	S-PQCC-J28
JESD-609代码	e3
长度	11.48 mm
逻辑集成电路类型	PARITY GENERATOR/CHECKER
位数	12
功能数量	1
端子数量	28
最高工作温度	85 °C
最低工作温度
输出极性	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装形状	SQUARE
封装形式	CHIP CARRIER
传播延迟（tpd）	0.95 ns
认证状态	Not Qualified
座面最大高度	4.57 mm
表面贴装	YES
技术	ECL
温度等级	COMMERCIAL EXTENDED
端子面层	MATTE TIN
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
宽度	11.48 mm
Base Number Matches	1

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Micrel, Inc.

12-BIT PARITY

GENERATOR/CHECKER

SY10E160

SY100E160

SY10E160

SY100E160

FEATURES

Provides odd-HIGH parity of 12 inputs

Extended 100E V

range of –4.2V to –5.5V

Output register with Shift/Hold capability

900ps max. D to Q, /Q output

Enable control

Asynchronous Register Reset

DESCRIPTION

The SY10/100E160 are high-speed, 12-bit parity

generator/checkers with differential outputs, for use in

new, high-performance ECL systems. The output Q takes

on a logic HIGH value only when an odd number of inputs

are at a logic HIGH. A logic HIGH on the enable input (EN)

forces the output Q to a logic LOW.

An additional feature of the E160 is the output register.

Two multiplexers and their associated signals control the

data, loading the new parity data or shifting external data

in. To hold the present data, the Hold signal (HOLD) must

be at a logic LOW level. If the HOLD signal is at a logic

HIGH, the data present at the Q output is passed through

the first multiplexer. Taking the Shift signal (SHIFT) to a

logic HIGH will shift the data at the S-IN pin into the output

of the first multiplexer is then passed through to the register.

The register itself is clocked on the rising edge of CLK

or CLK

(or both). The presence of a logic HIGH on the

reset pin (R) forces the register output Y to a logic LOW.

Differential outputs

Fully compatible with industry standard 10KH,

100K ECL levels

Internal 75K

Ω

input pulldown resistors

Fully compatible with Motorola MC10E/100E160

Available in 28-pin PLCC package

BLOCK DIAGRAM

HOLD

S-IN

SHIFT

CLK

MUX

SEL

MUX

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Rev.: F

Amendment: /0

Issue Date: March 2006

SY100E160JZ相似产品对比

	SY100E160JZ	SY10E160JC	SY100E160JC	SY10E160JZ
描述	Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28	Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28	Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, PLASTIC, LCC-28	Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28
厂商名称	Micrel ( Microchip )	Micrel ( Microchip )	Micrel ( Microchip )	Micrel ( Microchip )
包装说明	QCCJ,	PLASTIC, LCC-28	PLASTIC, LCC-28	QCCJ,
Reach Compliance Code	unknown	not_compliant	not_compliant	compli
系列	100E	10E	100E	10E
JESD-30 代码	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609代码	e3	e0	e0	e3
长度	11.48 mm	11.48 mm	11.48 mm	11.48 mm
逻辑集成电路类型	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
位数	12	12	12	12
功能数量	1	1	1	1
端子数量	28	28	28	28
最高工作温度	85 °C	85 °C	85 °C	85 °C
输出极性	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	QCCJ	QCCJ	QCCJ	QCCJ
封装形状	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
传播延迟（tpd）	0.95 ns	0.95 ns	0.95 ns	0.95 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	4.57 mm	4.57 mm	4.57 mm	4.57 mm
表面贴装	YES	YES	YES	YES
技术	ECL	ECL	ECL	ECL
温度等级	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
端子面层	MATTE TIN	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)
端子形式	J BEND	J BEND	J BEND	J BEND
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	QUAD	QUAD	QUAD	QUAD
宽度	11.48 mm	11.48 mm	11.48 mm	11.48 mm
是否Rohs认证	-	不符合	不符合	符合
湿度敏感等级	-	1	1	2
峰值回流温度（摄氏度）	-	240	240	260
处于峰值回流温度下的最长时间	-	30	30	NOT SPECIFIED

SY100E160JZ

SY100E160JZ概述

SY100E160JZ规格参数

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SY100E160JZ相似产品对比

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