HANBit
HSD64M64F8KA
Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on
32Mx8 ,4Banks, 4K Ref., 3.3V
GENERAL DESCRIPTION
The HSD64M64F8KA is a 64M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists
of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 120-pin glass-epoxy.
One 0.22uF and two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM.
The HSD64M64F8KA is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory
system applications All module components may be powered from a single 3.3V DC power supply and all inputs and
outputs are LVTTL-compatible.
Part No. HSD64M64F8KA
FEATURES
•
Part Identification
HSD64M64F8KA
–
10L : 100MHz (CL=3)
HSD64M64F8KA
–
10 : 100MHz (CL=2)
HSD64M64F8KA
–
13 : 133MHz (CL=3)
•
Burst mode operation
•
Auto & self refresh capability (8192Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going
edge of the system clock
•
The used device is stacked 8M x 8bit x 4Banks
SDRAM
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PIN ASSIGNMENT
60-PIN P1 Connector
Symbol
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
DQM4
DQM5
NC
CKE0
CKE1
Vcc
NC
NC
/CS1
/CS2
Vcc
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQM0
DQM1
/WE
CLK0
CLK1
Vss
/CAS
/RAS
/CS1
/CS2
Vss
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
60-PIN P2 Connector
Symbol
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQM2
DQM3
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vss
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
Vcc
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vcc
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vcc
DQM6
DQM7
A12
A11
A9
A8
A7
A6
A5
A4
Vcc
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
1
HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
Stacking
의
상 위
부분 위 치
HSD64M64F8KA
* /CS0 + /CS2(b'd) = /CS1(Module), /CS1 + /CS3(b'd) = /CS2(Module)
** Address (0:12), /RAS, /CAS, /WE, BA(0:1), CLK, CKE0
U0~U15
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REV. 1.0 (August, 2002)
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PIN FUNCTION DESCRIPTION
Pin
CLK
/CS
Name
System clock
Chip enable
Input Function
HSD64M64F8KA
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column address
strobe
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
/WE
Write enable
DQM0 ~ 7
Data input/output
mask
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
DQ0 ~ 63
Vcc/Vss
Data input/output
Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
16W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
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HANBit Electronics Co.,Ltd.
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DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
HSD64M64F8KA
UNIT
V
V
V
V
V
NOTE
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
DESCRIPTION
Input capacitance(A0~A11)
Input capacitance(/RAS, /CAS,/WE)
Input capacitance(CKE0)
Input capacitance(CLK0)
Input capacitance(/CS0~/CS3)
Input capacitance(DQM0~DQM7)
Input capacitance(BA0~BA1)
Data input/output capacitance (DQ0 ~ DQ63)
(Vcc = 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN3
C
IN3
C
OUT
MIN
40
40
40
40
40
40
40
64
MAX
80
80
80
64
80
64
64
104
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C)
TEST
PARAMETER
Operating current
(One bank active)
Precharge standby
current in
power-down mode
I
CC2
PS
I
CC1
I
CC2
P
SYMBOL
CONDITION
Burst length = 1
t
RC
≥
t
RC
(min) I
O
= 0mA
CKE
≤
V
IL
(max) t
CC
=10ns
CKE & CLK
≤
V
IL
(max)
t
CC
=∞
-10
720
-10L
720
16
16
-13
800
mA
mA
mA
VERSION
UNIT
E
1
3
3
NOT
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
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HANBit Electronics Co.,Ltd.
HANBit
CKE
≥
V
IH
(min)
I
CC2
N
/CS
≥
V
IH
(min),
tcc=10ns
320
HSD64M64F8KA
Precharge standby
current in
non power-down mode
Input signals are changed
one time during 20ns
CKE
≥
V
IH
(min)
mA
3
I
CC2
NS
CLK
≤
V
IL
(max),
tcc=∞
112
Input signals are stable
Active standby current in
power-down mode
I
CC3
P
I
CC3
PS
CKE
≤
V
IL
(max), tcc=10ns
CKE&CLK
≤
V
IL
(max) tcc=∞
CKE≥V
IH
(min),
I
CC3
N
/CS≥V
IH
(min),
tcc=10ns
480
mA
3
80
mA
80
3
Active standby current in
non power-down mode
(One bank active)
Input signals are changed
one time during 20ns
CKE≥VIH(min)
I
CC3
NS
CLK
≤VIL(max),
tcc=∞
320
Input signals are stable
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
I
O
= 0 mA Page burst
4Banks Activated
t
CCD
= 2CLKs
I
CC5
I
CC6
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
1520
1520
24
1600
mA
mA
2
3
800
800
880
mA
1
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1PLL & 3 Drive Ics.
4. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V
±
0.3V, T
A
= 0 to 70°C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
ns
V
URL:www.hbe.co.kr
REV. 1.0 (August, 2002)
5
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