HANBit
HSD64M64F8K
Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on
32Mx8, 4Banks, 4K Ref., 3.3V
GENERAL DESCRIPTION
The HSD64M64F8K is a 64M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists
of
sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin
TSSOP package on a 120-pin glass-epoxy. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM. The HSD64M64F8k is a SMM(Stackable Memory Module
type) .Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a
variety of high bandwidth, high performance memory system applications All module components may be powered from a
single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
Part No. HSD64M64F8K
FEATURES
•
Part Identification
HSD64M64F8K : 100MHz (CL=2)
•
Burst mode operation
•
Auto & self refresh capability (4096 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock
•
The used device is 8M x 8bit x 4Banks SDRAM
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 1
-
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
P1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
Vcc
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Vcc
DQM4
DQM5
REGE
CKE0
NC
Vcc
SDA
SCL
/CS2
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
/CS3
Vcc
Vss
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Vss
DQM0
DQM1
/WE
CLK0
CLK1
Vss
/CAS
PIN
57
58
59
60
Symbol
/RAS
/CS0
/CS1
Vss
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
Vss
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQM2
DQM3
NC
BA0
BA1
A10
A0
A1
A2
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
P2
HSD64M64F8K
Symbol
A3
Vss
Vcc
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vcc
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vcc
DQM6
DQM7
A12
A11
A9
A8
A7
PIN
57
58
59
60
Symbol
A6
A5
A4
Vcc
* These pins are not used in this module
*Pin Names
A0~A12: Address input (Multiplexed)
DQ0~DQ63: Data input/output
CLK0: Clock input
/CS0~/CS3: Chip select input
/CAS: Coulmn address strobe
DQM0~7: DQM
V
SS
: Ground
REGE: Register enable
SCL: Serial clock
WP: Write protection
NC: No connection
URL:www.hbe.co.kr
REV.1.0 (August.2002)
** These pins should be NC in the system which does not support SPD
BA0~BA1: Select bank
CKE0: Clock enable input
/RAS: Row address strobe
/WE: Write enable
Vcc: Power supply(3.3V)
*V
REF
:Power supply for reference
SDA: Serial data I/O
SA0~2: Address in EEPROM
DU: Don’t use
- 2
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HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
Upper
components
of
HSD64M64F8K
Stacked chips
A11-A12, BA1
A11
B
0
A11-B
0
A12, B
0
BA1
B
1
A11-B
1
A12, B
1
BA1
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 3
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HANBit Electronics Co.,Ltd.
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PIN FUNCTION DESCRIPTION
Pin
CLK
/CE
Name
System clock
Chip enable
Input Function
Active on the positive going edge to sample all inputs.
HSD64M64F8K
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
0.1uF or 0.22uF Capacitor
for each DRAM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column
strobe
/WE
Write
enable
address
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
Data
mask
REGE
Register enable
input/output
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is
high, the
device operates in the registered mode. In registered mode, the Address and
control inputs are latched if CLK is held at a high or low logic level. The inputs are
strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to V
DD
through 10K ohm register on PCB. So if REGE of module is floating, this module
will be operated as registerd mode.
DQ0 ~ 63
WP
Data input/output
Write Protection
Data inputs/outputs are multiplexed on the same pins.
WP pin is connected to Vcc.
When WP is
“high”
EEPROM Programming will be inhibited and the entire
,
memory will be write-protected.
Vcc/Vss
Power
supply/ground
Power and ground for the input buffers and the core logic.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 4
-
HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
HSD64M64F8K
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
16W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
NOTE
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
DESCRIPTION
Input capacitance(A0~A12)
Input capacitance(/RAS, /CAS,/WE)
Input capacitance(CKE0)
Input capacitance(CLK0)
Input capacitance(/CE0~/CE3)
Input capacitance(DQM0~DQM7)
Input capacitance(BA0~BA1)
Data input/output capacitance (DQ0 ~ DQ63)
(Vcc = 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN3
C
IN3
C
OUT
MIN
40
40
40
40
40
40
40
64
MAX
80
80
80
64
80
80
80
104
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 5
-
HANBit Electronics Co.,Ltd.
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