Philips Semiconductors
Product specification
Low cost dual frequency synthesizer for
radio telephones
FEATURES
•
Low phase noise
•
Low current from 3 V supply
•
Fully programmable dividers
•
3-line serial interface bus
•
Input reference buffer configurable as an oscillator with
external crystal resonator
•
Wide compliance voltage charge pump outputs
•
Two power-down input control pins.
APPLICATIONS
•
900 MHz and 2 GHz digital radio telephones
•
Portable battery-powered radio equipment.
GENERAL DESCRIPTION
The UMA1022M BICMOS device integrates prescalers,
programmable dividers, a crystal oscillator/buffer and
phase comparators to implement two phase-locked loops.
The device is designed to operate from 3 NiCd or a single
LiIon cell in pocket phones, or from an external 3 V supply.
UMA1022M
The synthesizers operate at RF input frequencies up to
2.1 GHz and 550 MHz. All divider ratios are supplied via a
3-wire serial programming bus. The reference divider uses
a common, fully programmable part and a separate
subdivider section. In this way the comparison frequencies
are related to each other allowing optimum isolation
between charge pump pulses.
Separate power and ground pins are provided to the
analog (charge pump, prescaler) and digital (CMOS)
circuits. An independent supply for the crystal oscillator
section allows maximum frequency stability. The ground
leads should be externally short-circuited to prevent large
currents flowing across the die and thus causing damage.
V
DD
and V
DDX
must be at the same potential. V
CCA
and
V
CCB
must be equal to each other and equal to or greater
than V
DD
(e.g. V
DD
= 3 V and V
CCA
= 5.5 V for wider VCO
control voltage range).
The charge pump currents (phase detector gain) are fixed
by internal resistances and controlled by the serial
interface. Only passive loop filters are necessary;
the charge pumps function within a wide voltage
compliance range to improve the overall system
performance.
Suitable pin layout is chosen to minimize coupling and
interference between signals entering or leaving the chip.
QUICK REFERENCE DATA
SYMBOL
V
DD
V
DDX
I
tot
PARAMETER
digital supply voltage
crystal reference supply voltage
all supply currents
(I
DD
+ I
CCA
+ I
CCB
+ I
DDX
) in active
mode
CONDITIONS
V
CCA
= V
CCB
≥
V
DD
V
CCA
= V
CCB
≥
V
DD
V
DDX
= V
DD
E = 1; V
CCA
= V
CCB
= 3.0 V;
V
DDX
= V
DD
= 3.0 V
XON = 0
XON = 1
I
tot(pd)
f
RF
f
IF
f
xtal
f
PCmax
T
amb
total supply currents in power-down
mode
RF input frequency
IF input frequency
crystal reference oscillator frequency
maximum loop comparison frequency
operating ambient temperature
V
CCA
= V
CCB
≤
4.0 V
−
−
−
300
50
50
3
−
−30
14.65
15.9
40
−
−
−
−
2000
−
−
−
−
2100
550
400
20
−
+85
mA
mA
µA
MHz
MHz
MHz
MHz
kHz
°C
MIN.
2.7
2.7
2.7
TYP.
3.0
3.0
3.0
MAX.
5.5
5.5
5.5
UNIT
V
V
V
V
CCA
, V
CCB
analog supply voltages
1998 Dec 09
2
Philips Semiconductors
Product specification
Low cost dual frequency synthesizer for
radio telephones
PINNING
SYMBOL
XIN
XGND
XOUT
CP
B
V
CCB
IF
B
ON
B
DGND
E
DATA
CLK
V
DD
ON
A
AGND
RF
A
V
CCA
CP
A
XOUT
V
DDX
XIN
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
inverting crystal reference input
ground for crystal oscillator circuits
crystal oscillator buffer output
IF synthesizer charge pump output
analog supply to IF synthesizer
IF VCO main divider input
IF power-on input; ON
B
= HIGH
means IF synthesizer is active
digital circuits ground
programming bus enable input
programming bus data input
programming bus clock input
digital circuits supply voltage
RF power-on input; ON
A
= HIGH
means RF synthesizer is active
analog circuits ground
RF VCO main divider input
analog supply to RF synthesizer
RF synthesizer charge pump output
inverting oscillator buffer output
supply voltage to crystal oscillator
circuits
non-inverting crystal reference input
handbook, halfpage
UMA1022M
XIN
XGND
XOUT
CPB
VCCB
IFB
ONB
DGND
E
1
2
3
4
5
20 XIN
19 VDDX
18 XOUT
17 CPA
UMA1022M
6
7
8
9
16 VCCA
15
14
13
12
RFA
AGND
ONA
VDD
DATA 10
MGE626
11 CLK
Fig.2 Pin configuration.
1998 Dec 09
4
Philips Semiconductors
Product specification
Low cost dual frequency synthesizer for
radio telephones
FUNCTIONAL DESCRIPTION
Main dividers
The main dividers are clocked at pin RF
A
by the RF
oscillator signal and at pin IF
B
by the IF oscillator signal.
The inputs are AC coupled through external capacitors.
Input impedances are high, dominated by parasitic
package capacitances, so matching is off-chip.
The sensitive dividers operate with signal levels from
35 to 225 mV (RMS), at frequencies up to 2.1 GHz
(RF part) and up to 550 MHz (IF part). Both include
programmable bipolar prescalers followed by CMOS
counters. The RF main divider allows programmable ratios
from 512 to 65535; the IF blocks accept values between
128 and 16383.
Crystal oscillator
A fully differential low-noise amplifier/buffer is integrated
providing outputs to drive other circuits, and to build a
crystal oscillator; only needed are an external resonance
circuit and tuning elements (temperature compensation).
A bus controlled power-down mode disables the low-noise
amplifier to reduce current if not needed.
The normal differential input pins drive a clock buffer to
provide edges to the programmable reference divider at
frequencies up to 20 MHz. The inputs are AC coupled
through external capacitors, and operate with signals
down to 35 mV (RMS) and up to 0.5 V (RMS).
Various crystal oscillator structures can be built using the
amplifier. By coupling one output back to the appropriate
input through the resonator, and decoupling the other input
to ground, the second output becomes available to deliver
the reference frequency to other circuits.
Reference dividers
A first common divider circuit produces an output
frequency for RF or IF synthesizer phase comparison,
depending on the P/A bit. It drives a second independent
divider, which delivers the reference edge to the IF or RF
synthesizer phase comparator. When P/A is logic 1, the
output of the subdivider is connected to the RF phase
comparator, whereas the output of the common divider is
connected to the IF phase detector.
The phase comparators run at related frequencies with a
controlled phase difference to avoid interference when
in-lock. The common 10-bit section permits divide ratios
from 8 to 1023; the second subdivider allows phase
comparison frequency ratios between 1 and 16. Table 2
indicates how to program the corresponding bits to get the
wanted ratio.
1998 Dec 09
5
Phase comparators
UMA1022M
The phase detectors are driven by the output edges
selected by the main and reference dividers. Each
generates lead and lag signals to control the appropriate
charge pump. The pumps output current pulses appear at
pins CP
A
(RF synthesizer) and CP
B
(IF synthesizer).
The current pulse duration is at least equal to the
difference in time of arrival of the edges from the two
dividers. If the main divider edge arrives first, CP
A
or CP
B
sink current. If the reference divider edge arrives first, CP
A
or CP
B
source current. For correct PLL operation the
VCOs need to have a positive frequency/voltage control
slope.
The currents at CP
A
and CP
B
are programmed via the
serial bus as multiples of an internally-set reference
current. The passage into power-down mode is
synchronized with respect to the phase detector to prevent
output current pulses being interrupted. Additional circuitry
is included to ensure that the gain of the phase
comparators remains linear even for small phase errors.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, clock (CLK) and enable
(E). The data sent to the device is loaded in bursts framed
by E. Programming clock edges and their appropriate data
bits are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns HIGH. During normal operation, E should be kept
HIGH. Only the last 19 bits serially clocked into the device
are retained within the programming register.
Additional leading bits are ignored, and no check is made
on the number of clock pulses. The NMOS-rich design
uses virtually no current when the bus is inactive;
power-up is initiated when enable is taken LOW, and
power-down occurs a short time after enable returns
HIGH. Bus activity is allowed when either synthesizer is
active or in power-down (ON
A
and ON
B
inputs LOW)
mode. Fully static CMOS registers retain programmed
data whatever the power-down state, as long as the supply
voltage is present.
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