Philips Semiconductors
Product specification
Low-voltage frequency synthesizer
for radio telephones
FEATURES
•
Low phase noise
•
Low current from 3 V supply
•
Fully programmable main divider
•
3-line serial interface bus
•
Independent fully programmable reference divider,
driven from external crystal oscillator
•
Dual charge pump outputs
•
Hard and soft power-down control.
APPLICATIONS
•
900 MHz and 2 GHz mobile telephones
•
Portable battery-powered radio equipment.
GENERAL DESCRIPTION
The UMA1021M BICMOS device integrates a prescaler,
programmable dividers, and a phase comparator to
implement a phase-locked loop.
QUICK REFERENCE DATA
SYMBOL
V
DD
V
CC
I
DD
+ I
CC
f
RF
f
xtal
f
PC
T
amb
PARAMETER
digital supply voltage
charge-pump supply voltage
supply current
RF input frequency
crystal reference input frequency
phase comparator frequency
operating ambient temperature
CONDITIONS
V
DD1
= V
DD2
;
V
CC
≥
V
DD
V
CC
≥
V
DD
MIN.
2.7
2.7
−
−
300
3
−
−30
−
−
10
5
−
−
200
−
TYP.
UMA1021M
The device is designed to operate from 3 NiCd cells, in
pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at RF input frequencies up to
2.2 GHz, with a fully programmable reference divider.
All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the
analog (charge-pump) and digital circuits. The ground
leads should be externally short-circuited to prevent large
currents flowing across the die and thus causing damage.
V
DD1
and V
DD2
must also be at the same potential (V
DD
).
V
CC
must be equal to or greater than V
DD
(e.g. V
DD
= 3 V
and V
CC
= 5 V for wider VCO control voltage range).
The phase detector has two charge-pump outputs, CP and
CPF, the latter of which is enabled directly at pin FAST.
This permits the design of adaptive loops. The charge
pump currents (phase detector gain) are fixed by an
external resistance at pin I
SET
and via the serial interface.
Only a passive loop filter is necessary; the charge pumps
function within a wide voltage compliance range to
improve the overall system performance.
MAX.
5.5
5.5
−
−
2200
35
−
+85
UNIT
V
V
mA
µA
MHz
MHz
kHz
°C
I
CC(pd)
+ I
DD(pd)
total supply current in power-down mode
ORDERING INFORMATION
TYPE
NUMBER
UMA1021M
PACKAGE
NAME
SSOP20
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
VERSION
SOT266-1
1999 Jun 17
2
Philips Semiconductors
Product specification
Low-voltage frequency synthesizer
for radio telephones
PINNING
SYMBOL
FAST
CPF
CP
V
DD2
V
SS3
RFI
V
SS2
POL
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
enable input for fast charge-pump
output CPF
fast charge-pump output
normal charge-pump output
power supply 2
ground 3
2 GHz main divider input
ground 2
digital input to select polarity of
power-on inputs (PON and sPON):
POL = 0 for active LOW and
POL = 1 for active HIGH
power-on input
ground 1
programming bus clock input
programming bus data input
programming bus enable input
power supply 1
complementary crystal frequency
input from TCXO; if not used should
be decoupled to ground
crystal frequency input from TCXO;
if not used should be decoupled to
ground
ground for charge-pump
supply for charge-pump
external resistor from this pin to
ground sets the charge-pump
currents
out-of-lock detector output
Reference divider
handbook, halfpage
UMA1021M
FAST
CPF
CP
VDD2
VSS3
RFI
VSS2
POL
PON
1
2
3
4
5
20 LOCK
19 ISET
18 VCC
17 GND(CP)
16 XTALA
PON
V
SS1
CLK
DATA
E
V
DD1
XTALB
9
10
11
12
13
14
15
UMA1021M
6
7
8
9
15 XTALB
14 VDD1
13 E
12 DATA
11 CLK
MBG365
VSS1 10
XTALA
16
GND(CP)
V
CC
I
SET
17
18
19
Fig.2 Pin configuration.
LOCK
20
FUNCTIONAL DESCRIPTION
Main divider
The main divider is clocked at pin RFI by the RF signal
which is AC-coupled from an external VCO. The divider
operates with signal levels from 50 to 225 mV (RMS), and
at frequencies from 300 MHz to 2.2 GHz. It consists of a
fully programmable bipolar prescaler followed by a CMOS
counter. Any divide ratios from 512 to 131071 inclusive
can be programmed.
The reference divider is clocked by the differential signal
between pins XTALA and XTALB. If only one of these
inputs is used, the other should be decoupled to ground.
The applied input signal(s) should be AC-coupled.
The circuit operates with levels from
50 up to 500 mV (RMS) and at frequencies from
3 to 35 MHz. Any divide ratios from 8 to 2047 inclusive
can be programmed.
1999 Jun 17
4
Philips Semiconductors
Product specification
Low-voltage frequency synthesizer
for radio telephones
Phase detector
The phase detector is driven by the output edges of the
main and reference dividers. It produces current pulses at
pins CP and CPF whose amplitudes are programmed.
The pulse duration is equal to the difference in time of
arrival of the edges from the two dividers. If the main
divider edge arrives first, CP and CPF sink current. If the
reference divider edge arrives first, CP and CPF source
current.
The currents at CP and CPF are programmed via the serial
bus as multiples of a reference current set by an external
resistor connected between pin I
SET
and V
SS
(see Table 3). CP remains active except in power-down.
CPF is enabled via input pin FAST which is synchronized
with respect to the phase detector to prevent output
current pulses being interrupted. By appropriate
connection to the loop filter, dual bandwidth loops can be
designed; short time constant during frequency switching
(FAST mode) to speed-up channel changes, and low
bandwidth in the settled state to improve noise and
breakthrough levels.
Additional circuitry is included to ensure that the gain of the
phase detector remains linear even for small phase errors.
Out-of-lock detector
The out-of-lock detector is enabled (disabled) via the serial
interface by setting bit OOL HIGH (LOW). An open drain
transistor drives the output pin LOCK (pin 20). It is
recommended that the pull-up resistor from this pin to V
DD
is chosen to be of sufficient value to keep the sink current
in the LOW state to below 400
µA.
When the out-of-lock
detector is enabled, LOCK is HIGH if the error at the phase
detector input is less than approximately 25 ns, otherwise
LOCK is LOW. If the out-of-lock detector is disabled,
LOCK remains HIGH.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, clock (CLK) and enable
(E). The data sent to the device is loaded in bursts framed
by E. Programming clock edges and their appropriate data
bits are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns HIGH.
UMA1021M
During normal operation, E should be kept HIGH. Only the
last 21 bits serially clocked into the device are retained
within the programming register. Additional leading bits
are ignored, and no check is made on the number of clock
pulses. The fully static CMOS design uses virtually no
current when the bus is inactive. It can always capture new
programmed data even during power-down.
When the synthesizer is powered-on, the presence of a
TCXO signal at the reference divider input and a VCO
signal at the main divider input is
required
for correct
programming.
Data format
The leading bits (dt16 to dt0) make up the data field, while
the trailing four bits (ad3 to ad0) are the address field.
The UMA1021M uses 4 of the 16 available addresses.
These are chosen for compatibility with other Philips
Semiconductors radio telephone ICs. The data format is
shown in Table 1. The first bit entered is dt16, the last bit
is ad0. For the divider ratios, the first bits entered (PM16
and PR10) are the most significant (MSB).
The trailing address bits are decoded on the rising edge of
E. This produces an internal load pulse to store the data in
the addressed latch. To avoid erroneous divider ratios,
the load pulse is not allowed during data reads by the
frequency dividers. This condition is guaranteed by
respecting a minimum E pulse width after data transfer.
The test register (address 0000) does not normally need to
be programmed. However if it is programmed, all bits in the
data field should be set to logic 0.
Power-down mode
The synthesizer is on when both the input signals PON
and the programmed bit sPON are active. The ‘active’ level
for these two signals is chosen at pin POL (see Table 2).
When turned on, the dividers and phase detector are
synchronized to avoid random phase errors. When turned
off, the phase detector is synchronized to avoid
interrupting charge-pump pulses. For synchronisation
functions to work correctly on power-up or power-down
(using either hardware or software programming), the
presence of TCXO and VCO signals is required to drive
the appropriate divider inputs. The UMA1021M has a very
low current consumption in the power-down mode.
1999 Jun 17
5
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