Supports control, interrupt, bulk, and isochronous
transfers for all 16 endpoints.
Programmable endpoint types and FIFO sizes and
internal 1120-byte logical (2240-byte physical for
dual-packet mode) shared FIFO storage allow a
wide variety of configurations.
Dual-packet mode of FIFOs reduces latency.
Supports USB remote wake-up feature.
On-chip crystal oscillator allows external 12 MHz
crystal or 3 V/5 V clock source.
On-chip analog PLL creates 48 MHz clock from
internal 12 MHz clock.
Integrated USB transceivers.
5 V tolerant I/O buffers allow operation in 3 V or
5 V system environments for 0 °C to 70 °C temper-
ature range.
5 V tolerant I/O buffers allow operation in 3 V only
system environments for –20 °C to +85 °C temper-
ature range.
Implemented in Agere Systems Inc. 0.25
µm,
3 V
standard-cell library.
44-pin MQFP (USS820D)
(lead-free package also
available). (See Ordering Information on page 52.)
Evaluation kit available.
New Features After Revision B
New, centralized FIFO status bits and interrupt out-
put pin reduce firmware load.
New, additional nonisochronous transmit mode
allows NAK response to cause interrupt.
Isochronous behavior enhancements simplify firm-
ware control.
Additional FIFO sizes for nonisochronous end-
points.
USB RESET can be programmed to clear device
address.
USB RESET output status pin.
Firmware ability to wake up and reset a suspended
device.
Lower power.
5 V supply no longer required for 5 V tolerant oper-
ation.
Applications
Suitable for peripherals with embedded micropro-
cessors.
Glueless interface to microprocessor buses.
Support of multifunction USB implementations,
such as printer/scanner and integrated multimedia
applications.
Suitable for a broad range of device class peripher-
als in the USB standard.
Note:
Advisories are issued as needed to update
product information. When using this data
sheet for design purposes, please contact
your Agere Systems Account Manager to
obtain the latest advisory on this product.
USS820D
USB 2.0 Full-Speed Device Controller
Data Sheet, Rev. 8
November 2005
Table of Contents
Contents
Page
Features ....................................................................................................................................................................1
New Features After Revision B .................................................................................................................................1
Serial Interface Engine............................................................................................................................................ 3
FIFO Control ........................................................................................................................................................... 4
Pin Information .........................................................................................................................................................7
Special Firmware Action for Shared Register Bits ................................................................................................ 13
Register Reads with Side Effects.......................................................................................................................... 14
Firmware Responsibilities for USB SETUP Commands..........................................................................................41
Other Firmware Responsibilities..............................................................................................................................42
USB Application Support Contact Information.........................................................................................................46
Absolute Maximum Ratings.....................................................................................................................................46
dc Characteristics ................................................................................................................................................. 47
Power Considerations ........................................................................................................................................... 48
USB Transceiver Driver Characteristics ............................................................................................................... 48
USB Transceiver Connection ............................................................................................................................. 49
Appendix A. Special Function Register Bit Names..................................................................................................53
Appendix B. USS820D Register Map......................................................................................................................54
Appendix C. Changes from USS820/USS-825 Revision B to C..............................................................................55
Appendix D. Changes from USS820/USS820T Revision C to D ............................................................................56
2
Agere Systems Inc.
Data Sheet, Rev. 8
November 2005
USS820D
USB 2.0 Full-Speed Device Control-
Description
USS820D
PLL
OSCILLATOR
DPLS
DMNS
V
SS
V
DD
USB
XCVR
DIGITAL
PLL
SIE
PROTOCOL
LAYER
FIFO
CONTROL
EXTERNAL
MICROPROCESSOR
BUS
FIFOs
5-8121
Figure 1. Block Diagram
USS820D is a USB device controller that provides a
programmable bridge between the USB and a local
microprocessor bus. It is available in a 44-pin MQFP
package. The USS820D allows PC peripherals to
upgrade to USB connectivity without major redesign
effort. It is programmable through a simple read/write
register interface that is compatible with industry-stan-
dard USB microcontrollers.
USS820D is designed in 100% compliance with the
USB industry standard, allowing device-side USB prod-
ucts to be reliably installed using low-cost, off-the-shelf
cables and connectors.
The integrated USB transceiver supports 12 Mbits/s
full-speed operation. FIFO options support all four
transfer types: control, interrupt, bulk, and isochronous,
as described in
Universal Serial Bus Specification
Revision 2.0,
with a wide range of packet sizes. Its
double sets of FIFO enable the dual-packet mode
feature. The dual-packet mode feature reduces latency
by allowing simultaneous transfers on the host and
microprocessor sides of a given unidirectional
endpoint.
The USS820D supports a maximum of eight bidirec-
tional endpoints with 16 FIFOs (eight for transmit and
eight for receive) associated with them. The FIFOs are
on-chip, and sizes are programmable up to a total of
1120 logical bytes. When the dual-packet mode feature
is enabled, the device uses a maximum of 2240 bytes
of physical storage. This additional physical FIFO stor-
age is managed by the device hardware and is trans-
parent to the user.
The FIFO sizes supported are 8 bytes, 16 bytes,
32 bytes, and 64 bytes for nonisochronous pipes, and
64 bytes, 256 bytes, 512 bytes, and 1024 bytes for iso-
chronous pipes. The FIFO size of a given endpoint
defines the upper limit to maximum packet size that the
hardware can support for that endpoint. This flexibility
covers a wide range of data rates, data types, and com-
binations of applications.
The USS820D can be clocked either by connecting a
12 MHz crystal to the XTAL1 and XTAL2 pins, or by
using a 12 MHz external oscillator. The internal 12 MHz
clock period, which is a function of either of these clock
sources, is referred to as the device clock period (t
CLK
)
throughout this data sheet.
Serial Interface Engine
The SIE is the USB protocol interpreter. It serves as a
communicator between the USS820D and the host
through the USB lines.
The SIE functions include the following:
Package protocol sequencing.
SOP (start of packet), EOP (end of packet),
RESUME, and RESET signal detection and genera-
tion.
NRZI data encoding/decoding and bit stuffing.
CRC generation and checking for token and data.
Serial-to-parallel and parallel-to-serial data conver-
sion.
Agere Systems Inc.
3
USS820D
USB 2.0 Full-Speed Device Controller
Data Sheet, Rev. 8
November 2005
Each FIFO can be programmed independently via the
TXCON and RXCON registers, but the total logical size
of the enabled endpoints (TX FIFOs + RX FIFOs) must
not exceed 1120 bytes. The 1120-byte total allows a
configuration with a full-sized, 1024-byte isochronous
endpoint, a minimum-sized, 64-byte isochronous feed-
back endpoint, and the required, bidirectional, 16-byte
control endpoint. When the dual-packet mode feature is
enabled, the device uses a maximum of 2240 bytes of
physical storage. This additional physical FIFO storage
is managed by the device hardware and is transparent
to the user.
Description
(continued)
Protocol Layer
The protocol layer manages the interface between the
SIE and FIFO control blocks. It passes all USB OUT
and SETUP packets through to the appropriate FIFO. It
is the responsibility of firmware to correctly interpret
and execute each USB SETUP command (as docu-
mented in the Firmware Responsibilities for USB
SETUP Commands section) via the register interface.
The protocol layer tracks the setup, data, and status
stages of control transfers.
FIFO Access
FIFO Control
USS820D’s FIFO control manager handles the data
flow between the FIFOs and the device controller’s pro-
tocol layer. It handles flow control and error handling/
fault recovery to monitor transaction status and to relay
control events via interrupt vectors.
The transmit and receive FIFOs are accessed by the
application through the register interface (see
Tables
22—25
for transmit FIFO registers and
Tables
26—29
for receive FIFO registers).
The transmit FIFO is written to via the TXDAT register,
and the receive FIFO is read via the RXDAT register.
The particular transmit/receive FIFO is specified by the
EPINDEX register. Each FIFO is accessed serially,
each RXDAT read increments the receive FIFO read
pointer by 1, and each TXDAT write increments the
transmit FIFO write pointer by 1.
Each FIFO consists of two data sets to provide the
capability for simultaneous read/write access. Control
of these pairs of data sets is managed by the hardware,
invisible to the application, although the application
must be aware of the implications. The receive FIFO
read access is advanced to the next data set by firm-
ware setting the RXFFRC bit of RXCON. This bit clears
itself after the advance is complete. The transmit FIFO
write access is advanced to the next data set by firm-
ware writing the byte count to the TXCNTH/L registers.
The USB access to the receive and transmit FIFOs is
managed by the hardware, although the control of the
nonisochronous data sets can be overridden by the
ARM and ATM bits of RXCON and TXCON, respec-
tively. A successful USB transaction causes FIFO
access to be advanced to the next data set. A failed
USB transaction (e.g., for receive operations, FIFO
overrun, data time-out, CRC error, bit stuff error; for
transmit operations, FIFO underrun, no ACK from host)
causes the FIFO read/write pointer to be reversed to
the beginning of the data set to allow transmission retry
for nonisochronous transfers.
FIFO Programmability
Table 1
shows the programmable FIFO sizes. The size
of the FIFO determines the maximum packet size that
the hardware can support for a given endpoint. An end-
point is only allocated space in the shared FIFO stor-
age if its RXEPEN/TXEPEN bit = 1. If the endpoint is
disabled (RXEPEN/TXEPEN = 0), it is allocated
0 bytes. Register changes that affect the allocation of
the shared FIFO storage among endpoints must not be
made while there is valid data present in any of the
enabled endpoints’ FIFOs. Any such changes will ren-
der all FIFO contents undefined. Register bits that
affect the FIFO allocation are the endpoint enable bits
(the TXEPEN and RXEPEN bits of EPCON), the size
bits of an enabled endpoint (FFSZ bits of TXCON and
RXCON), the isochronous bit of an enabled endpoint
(TXISO bit of TXCON and RXISO bit of RXCON), and
the FEAT bit of the MCSR register.
If the MCSR.FEAT register bit is set to 1, additional
FIFO sizes are enabled for nonisochronous endpoints,
as shown in
Table 1.
Table 1. Programmable FIFO Sizes
FFSZ[1:0]
00
01
10
11
Nonisoch- 16 bytes 64 bytes 8 bytes* 32 bytes*
ronous
Isochro-
64 bytes 256 bytes 512 bytes 1024 bytes
nous
* Assumes MCSR.FEAT = 1. If this bit is 0 and FFSZ = 10 or 11, both
indicate a size of 64 bytes.
4
Agere Systems Inc.
Data Sheet, Rev. 8
November 2005
USS820D
USB 2.0 Full-Speed Device Controller
Description
(continued)
FIFO Access
(continued)
Transmit FIFO
The transmit FIFOs are circulating data buffers that have the following features:
Support up to two separate data sets of variable sizes (dual-packet mode).
Include byte counter register for storing the number of bytes in the data sets.
Protect against overwriting data in a full FIFO.
Can retransmit the current data set.
All transmit FIFOs use the same architecture (see
Figure 2).
The transmit FIFO and its associated logic can man-
age up to two data sets: data set 0 (ds0) and data set 1 (ds1). Since two data sets can be used in the FIFO, back-
to-back transmissions are supported. Dual-packet mode for transmit FIFOs is enabled by default. Single-packet
mode can be enforced by firmware convention (see TXFIF register bits).
The CPU writes to the FIFO location that is specified by the write pointer. After a write, the write pointer automati-
cally increments by 1. The read marker points to the first byte of data written to a data set, and the read pointer
points to the next FIFO location to be read by the USB interface. After a read, the read pointer automatically incre-
ments by 1.
When a good transmission is completed, the read marker can be advanced to the position of the read pointer to set
up for reading the next data set. When a bad transmission is completed, the read pointer can be reversed to the
position of the read marker to enable the function interface to reread the last data set for retransmission. The read
marker advance and read pointer reversal can be achieved two ways: explicitly by firmware or automatically by
hardware, as indicated by bits in the transmit FIFO control register (TXCON).
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