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IS61SF25636D-9TQ

产品描述Cache SRAM, 256KX36, 9ns, CMOS, PQFP100, TQFP-100
产品类别存储    存储   
文件大小146KB,共21页
制造商Integrated Silicon Solution ( ISSI )
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IS61SF25636D-9TQ概述

Cache SRAM, 256KX36, 9ns, CMOS, PQFP100, TQFP-100

IS61SF25636D-9TQ规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Integrated Silicon Solution ( ISSI )
零件包装代码QFP
包装说明TQFP-100
针数100
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间9 ns
其他特性FLOW-THROUGH ARCHITECTURE
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度9437184 bit
内存集成电路类型CACHE SRAM
内存宽度36
功能数量1
端子数量100
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织256KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)240
电源3.3 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.03 A
最小待机电流3.14 V
最大压摆率0.35 mA
最大供电电压 (Vsup)3.63 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度14 mm
Base Number Matches1

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IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O for SF
• 2.5V I/O for LF
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
ISSI
®
PRELIMINARY INFORMATION
NOVEMBER 2000
DESCRIPTION
The
ISSI
IS61SF25632, IS61SF25636, IS61SF51218,
IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, secondary cache for the
Pentium™, 680X0™, and PowerPC™ microprocessors.
The IS61SF25632 and IS61LF25632 are organized as
262,144 words by 32 bits and the IS61SF25636 and
IS61LF25636 are organized as 262,144 words by 36 bits.
The IS61SF51218 and IS61LF51218 are organized as
524,288 words by 18 bits. Fabricated with
ISSI
's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers that are controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-8*
8
10
100
-8.5
8.5
11
90
-9
9
15
66
-10
10
15
66
Units
ns
ns
MHz
*This speed available only in SF version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
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