Features
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Designed in Accordance with CAN Specification 2.0B
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CAN 2.0B Protocol Functions
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4 Different Data Rates Using an Internal Programmable Prescaler
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– 1 Mbit/s, 500 kbit/s, 250 kbit/s, 125 kbit/s
16 MHz Cycle Frequency
Power-down: Sleep Mode
CAN Bus Line Arbitration
All Required CAN Functions:
Error Handling:
– Stuff Bit Generation
– CRC Generation
– Acknowledge Generation
– Remote Frame
1 TX Buffer and 3 RX Buffer
3 Individual Acceptance Filtering
Interrupt Outputs Can be Generated for the Following Events
– Telegram Sent Successfully
– Telegram Received Successfully
– Receive Buffer Overflow
– Bus Off Condition
– Error Passive Condition
Technology: Atmel MG2RTP Radiation Hardened Sea of Gate 0.5 um
Type: Semi-Custom Digital 5V
Operating Frequency: 16 MHz (Test Frequency is 10MHz)
Maximum Frequency: 18 MHz
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
Tested up to a Total Dose of 300 Krads(si) According to MIL STD 883 Method 1019
QML-Q and V with SMD 5962-03A06
Package: MLCC 44 pins
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CAN Controller
for Space
Application
AT7908E
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Description
The AT7908E is a CAN controller stand-alone device for space application. Redun-
dant structures and special techniques are implemented in order to make the device
SEU tolerant. The AT7908E CAN core provides all CAN 2.0B protocol functions
except the overload frame generation. It includes the acceptance filtering. The core
incorporates error-handling capabilities, the stuff bit generation, CRC, multiple sample
points and remote frame generation. The AT7908E provides a programmable MCU 8-
bit general-purpose interface to connect receive and transmit buffer, control register
and status register to CPU.
The AT7908E was designed by Aurelia Microelettronica S.p.A., Italy, and the chip is
known as CASA (CAN ASIC for Space Application).
4268D–AERO–11/09
1
Signal Pins Description
Pin Number
9
8
11
13
10
23
22
16
5, 4, 3, 2, 44, 43,
42, 41
38, 37, 36, 35, 33,
32, 31, 30
25
27
19
14
15
26
20
Signal
Name
Mode
Cs
Wr
Rd
ALE
Xtalin
Xtalout
Reset
addr<7:0>
Data<7:0>
Int
Can_tx
Can_rx
sena
test
hatrig
hasync
Type
I - CMOS
I - CMOS
I - CMOS
I - CMOS
I - CMOS
I - CMOS
IO - CMOS
I - CMOS
I - CMOS
IO - CMOS
O - CMOS
O - CMOS
I - CMOS
I - CMOS
I - CMOS
O - CMOS
O - CMOS
AH
AH
AH
AH
AL
AL
AH
AL
AL
AH
Note
Description
Interface operational mode
Chip select signal
Write signal
Read signal
Address latch enable
Input to internal oscillators or clock
input from external oscillator
Output from internal oscillator
reset signal
Input address(mode1) or output
address(mode 0)
Address data bus
interrupt request
tx signal
rx signal
scan enable
input signal to increase testability
Output signal to trigger the message
matching
Output synchronization signal
Note:
Abbreviations: O = output, I = input, IO = bi-directional I/O, AL = Active Low, AH = Active
High.
2
AT7908E
4268D–AERO–11/09
AT7908E
Oscillator
Xtalin and Xtalout are IOs of an internal inverting oscillator. To use the internal oscillator,
the quartz must be connected between Xtalin and Xtalout pins.
To drive the device with an external clock source, Xtalin must be driven by clock signal
and Xtalout must be left unconnected. The maximum operating frequency of the oscilla-
tor, in open-loop mode(without crystal) with 6 pF load on Xtalout at worst condition
(Process slow, temperature = 145°C, Power supply = 4.5V ) is 60 MHz.
The IO level of Xtalin and Xtalout are CMOS levels.
The internal clock could be put on off condition with external pins SENA = logical value
1 and TEST = logical value 0.
Reset Specification
The reset pin must be driven low for at least 3 clock cycles ( 190 ns at 16 MHz).
The reset signal must be driven low at power on of the AT7908E for at least 200 ns to
avoid abnormal start condition of the AT7908E device.
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4268D–AERO–11/09
Electrical Characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA)... Military –55 to +125°C
Junction temperature .....................................................175°C
Storage temperature .........................................–65 to +150°C
*NOTICE:
Stresses above those listed may cause perma-
nent damages to the device. Exposure to abso-
lute maximum rating conditions for extended
period may affect device reliability.
Power Dissipation: ..........................................0.3W
Themal Resistance Junction to Case: ...........5.1°C/W
TTL/CMOS :
Supply voltage ........................................... VDD –0.5V to +6V
I/O voltage ............................................. –0.5V to VDD + 0.5V
DC Characteristics
Specified at VDD = +5V +/– 10%
Symbol
VIL
VIH
VOL
VOH
IL
IOZ
IOS
Parameter
Input LOW voltage
CMOS input
Input HIGH voltage
CMOS input
Output LOW voltage
CMOS Output
Output HIGH voltage
CMOS Output
Input Leakage current
NO Pull up/down
3-State Output Leakage current
Output Short circuit current
IOSN
IOSP
24
18
mA
mA
+/- 1
+/-1
+/- 5
+/-5
mA
mA
BOUT6
VOUT = 4.5V
VOUT = VSS
3.9
V
0.4
V
0.7VDD
VDD
V
IOL = +6 mA
(1)
IOH = -6 mA
(1)
0
0.3VDD
V
Min
Typ
Max
Unit
Conditions
Note:
1. According to the following buffers: BOUT6, BIOC6 @ VDD = 4.5V
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AT7908E
4268D–AERO–11/09
AT7908E
AC Characteristics
Tj = 125 °C, Process typical (all values in ns)
Tp
Output Signals
Can_tx
Int
Hasync
Hatrig
Set up Data<7:0>/Ale
Hold Data<7:0>/Ale
BIOC6: Bi-directional Buffer
CMOS input
75 pF
BOUT6: Output buffer with 6
mA drive
75 pF
Buffer Description
Load
Xtalin to Output High
29
25
26
5
6
19
Tp
Xtalin to Output Low
Set Up
or Hold
Power Consumption
Parameter
DC Curent
Dissipation
Max
50 mA @ 5V
Min
-
Note
CLK frequency = 16 MHz
Technology
MG2RTP 0.5 mm 3 Metal Layers Sea of Gate.
Matrix: MG2 –044: 33K usable gates.
Package: MLCC_J44: Ceramic Multi layer Package
Application
The core architecture has been implemented taking into account the typical constraints
of a space application:
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No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
Tested up to a Total Dose of 300 Krads(si) According to MIL STD 883 Method 1019
Design using the SEU hardened flip flops
Sleep mode for low power consumption
Insertion of test structures (internal scan chain) to reach a fault coverage > 95%
according to ESA specification
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4268D–AERO–11/09
嵌入式系统
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