PRELIMINARY
VCXO JITTER ATTENUATOR &
FEMTOCLOCK™ MULTIPLIER
ICS813322-02
G
ENERAL
D
ESCRIPTION
The ICS813322-02 is a member of the
IC
S
HiperClockS™ family of high performance clock
HiPerClockS™
solutions from IDT. The ICS813322-02 is a PLL
based synchronous multiplier that is optimized for
Ethernet or SONET-to-SONET clock jitter atten-
uation and frequency translation. The device contains two
internal frequency multiplication stages that are cascaded in
series. The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency SONET output clock that meets up to SONET
OC-48 jitter requirements. Pre-divider and output divider
multiplication ratios are selected using device selection
control pins. The multiplication ratios are optimized to support
most common clock rates used in Ether net and SONET
applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive
loop filter components which allows configuration of the PLL
loop bandwidth and damping characteristics. The device is
packaged in a space-saving 32-VFQFN package.
F
EATURES
•
Two differential LVPECL outputs
Each output supports independent frequency selection at
19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
•
Two differential inputs support the following input types:
LVPECL, LVDS, HCSL
•
Accepts input frequencies from 8kHz to 156.25MHz including
8kHz,19.44MHz, 25MHz, 62.5MHZ, 77.76MHz, 125MHz,
155.52MHz and 156.25MHz
•
Each output has independently controlled dividers for
common SONET clock rates
•
Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
•
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
using external loop filter connection
•
FemtoClock frequency multiplier provides low jitter, high
frequency output
•
Absolute pull range: 50ppm
•
FemtoClock VCO frequency: 622.08MHz
•
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz – 20MHz): 1.16ps (typical)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
nCLK1
P
IN
A
SSIGNMENT
XTAL_OUT
XTAL_IN
nCLK0
CLK0
CLK1
V
CCX
V
CC
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
EE
CLK_SEL
V
CC
nc
V
EE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
ODBSEL_1
ODBSEL_0
V
CC
ODASEL_1
PDSEL_2
PDSEL_1
PDSEL_0
V
CCA
24
23
22
21
20
19
18
17
V
EE
nQB
QB
V
CCO
nQA
QA
V
EE
ODASEL_0
ICS813322-02
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
VCXO JITTER ATTENUATOR/MULTIPLIER
1
ICS813322BK-02 REV. B AUGUST 14, 2008
ICS813322-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7, 20, 23
9,
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
nc
PDSEL_2,
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Unused
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup
Description
Loop filter connection node pins.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1/nCLK1.
Pulldown
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
Core power supply pins.
No connect.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Bank A differential clock outputs. LVPECL interface levels.
Output power supply pin.
Bank B differential clock outputs. LVPECL interface levels.
Inver ting differential clock input. V
DD
/2 bias voltage when left floating.
Non-inver ting differential clock input.
Inver ting differential clock input. V
DD
/2 bias voltage when left floating.
Non-inver ting differential clock input.
Cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Power supply pin for VCXO charge pump.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
VCXO JITTER ATTENUATOR/MULTIPLIER
3
ICS813322BK-02 REV. B AUGUST 14, 2008
微控制器 MCU
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