SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
ICS840271I
General Description
The ICS840271I is a PLL-based Frequency
Translator intended for use in telecommunication
HiPerClockS™
applications such as Synchronous Ethernet. The
internal PLL translates Ethernet clock frequencies
such as 125MHz (1Gb Ethernet), 156.25MHz
(10GbE XAUI) and 161.1328MHz (10Gb Ethernet) to an output
frequency of 25MHz. The PLL does not any require external
components. The input frequency is selectable by a 2-pin
interface. The ICS840271I is optimized for low cycle-to-cycle jitter
on the 25MHz output signal. The input of the device accepts
differential (LVPECL, LVDS, LVHSTL, SSTL, HCSL) or
single-ended (LVCMOS) signals. The extended temperature range
supports telecommunication and networking equipment
requirements. The ICS840271I uses a small RoHS 6, 8-pin
TSSOP package and is an effective solution for space-constrained
applications.
Features
•
•
•
•
•
•
•
•
•
•
Clock frequency translator for Synchronous Ethernet
applications
One single-ended output (LVCMOS or LVTTL levels),
16Ω output impedance
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
Supports input clock frequencies of: 125MHz, 156.25MHz or
161.1328MHz
Generates a 25MHz output clock signal
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/LVTTL) input levels
Internal PLL is optimized for low cycle-to-cycle jitter at the
output
Full 3.3V or 2.5V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS
Block Diagram
CLK
nCLK
Pin Assignment
V
DDA
Pre-
divider
PLL
Feedback
divider
Output
divider
25 MHz
Q
SEL0
CLK
nCLK
1
2
3
4
8
7
6
5
V
DD
Q
GND
SEL1
SEL(1:0)
Input Control Logic
00 = PLL Bypass
01 = 161.1328125 MHz
10 = 156.2500000 MHz
11 = 125.0000000 MHz
ICS840271I
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™
SYN
CHRONOUS ETHERNET FREQUENCY TRANSLATOR
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ICS840271BGI REV. A APRIL 23, 2009
ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
V
DDA
SEL0
CLK
nCLK
SEL1
GND
Q
V
DD
Power
Input
Input
Input
Input
Power
Output
Power
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Type
Description
Analog supply pin.
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Selects the input reference frequency and the PLL bypass mode.
LVCMOS/LVTTL interface levels. See Table 3.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
V
DD
= 3.465V
V
DD
= 2.625V
16
19
Maximum
Units
pF
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
Ω
Ω
Function Tables
Table 3. SEL[1:0] Function Table
Inputs
SEL1
0
0
1 (default)
1
SEL0
0
1
0 (default)
1
CLK, nCLK (MHz)
REF
161.1328125
156.25
125
Mode
PLL Bypass
PLL Enabled
PLL Enabled
PLL Enabled
Output (MHz)
REF/ 5
25
25
25
NOTE: REF = Input clock signal frequency
IDT™ / ICS™
SYN
CHRONOUS ETHERNET FREQUENCY TRANSLATOR
2
ICS840271BGI REV. A APRIL 23, 2009
ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
129.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.08
Typical
3.3
3.3
Maximum
3.465
V
DD
75
8
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.08
Typical
2.5
2.5
Maximum
2.625
V
DD
72
8
Units
V
V
mA
mA
IDT™ / ICS™
SYN
CHRONOUS ETHERNET FREQUENCY TRANSLATOR
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ICS840271BGI REV. A APRIL 23, 2009
ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
SEL1
I
IH
Input High Current
SEL0
SEL1
I
IL
Input Low Current
SEL0
Output High Voltage
Output Low Voltage
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, I
OH
= 12mA
V
DD
= 2.625V, I
OH
= 12mA
V
DD
= 3.465V or 2.625V, I
OL
= -12mA
-150
-5
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IL
V
OH
V
OL
Table 4D. Differential DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current
CLK/nCLK
CLK
I
IL
Input Low Current
nCLK
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
IDT™ / ICS™
SYN
CHRONOUS ETHERNET FREQUENCY TRANSLATOR
4
ICS840271BGI REV. A APRIL 23, 2009
ICS840271I
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(cc))
t
LOCK
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
SEL0
≠
SEL1
SEL0 = SEL1 = 1
SEL1 = 0, SEL0 = 1
SEL 1 = 1, SEL0 = X
20% to 80%
200
47
Test Conditions
Minimum
Typical
25
40
15
1
50
700
53
Maximum
Units
MHz
ps
ps
s
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
Table 5B. AC Characteristics,
V
DD
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(cc))
t
LOCK
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
SEL0
≠
SEL1
SEL0 = SEL1 = 1
SEL1 = 0, SEL0 = 1
SEL 1 = 1, SEL0 = X
20% to 80%
200
47
Test Conditions
Minimum
Typical
25
50
15
1
50
700
53
Maximum
Units
MHz
ps
ps
s
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
IDT™ / ICS™
SYN
CHRONOUS ETHERNET FREQUENCY TRANSLATOR
5
ICS840271BGI REV. A APRIL 23, 2009
FPGA/CPLD
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