DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-40
Description
The ICS1894-40 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802-3.
The ICS1894-40 is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1894-40 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz. With this
IDT-patented technology, the ICS1894-40 can virtually
eliminate errors from killer packets.
The ICS1894-40 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-40
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of
10 Mb/s or 100Mb/s.
In addition, the ICS1894-40 includes a programmable
interupt output function. This function consists of a digital
output pin, an interrupt control register, a set of interrupt
status register bits and a corresponding set of interrupt
enable bits, and a pre-defined set of events which can be
assigned as one of the interrupt sources. The purpose of
this function is to notify the host of this PHY device when
certain event happens via interrupt (the logic level on
interrupt output pin going low or going high) instead of
polling by the host. The events that could be used to
generate interrupts are: receiver error, Jabber, page
received, parallel detect fault, link partner acknowledge, link
status change, auto-negotiation complete, remote fault,
collision, etc
Applications:
NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
•
Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
•
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
•
10Base-T and 100Base-TX IEEE 8802.3 compliant
•
MIIM (MDC/MDIO) management bus for PHY register
configuration
•
RMII interface support with external 50 MHz system clock
•
Single 3.3V power supply
•
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
Auto-MDI/MDIX crossover correction
•
•
•
•
•
Low-power CMOS (typically 300 mW)
Power-Down mode typically 21mW
Clock and crystal supported
Interrupt pin option
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
•
•
•
•
Single power supply (3.3 V)
Built-in 1.8 V regulator for core
Available in 40-pin (5mm x 5mm) QFN package, Pb-free
Available in Industrial Temp and Lead Free
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 1
ICS1894-40
REV C 092909
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 MII/RMII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P4/LED2
P1/LED1
P0/LED0
REFOUT
REFIN
AMDIX
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
1
31
VDDD
TXD3
TXD2
TXD1
VSS
LED3
TXD0
TXEN
SPEED/TXCLK
NOD/RXER
ANSEL/RXCLK
NLG40 Without Ground Connecting to
Thermal Pad
TXER
SPEED
RMII/RXDV
FDPX/RXD0
11
21
SI/LED4
HWSW/CRS
MDC
REGPIN/COL
AMDIXRXD3
40-pin MLF
40-pin 6mm x 6mm QFN
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 2
RXTR1RXD1
RESET_N
P2/INT
MDIO
P3/RXD2
VDDIO
ICS1894-40
REV C 092909
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin
Name
AMDIX
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
VSS
RESET_N
P2/INT
MDIO
MDC
VDDIO
HWSW/
CRS
Regpin/
COL
AMDIX/RXD3
P3/RXD2
RXTRI/
RXD1
SI/LED4
FDPX/
RXD0
RMII/RXDV
SPEED
TXER
ANSEL/
RXCLK9
NOD/
RXER
Pin
Type
IN/Ipu
AIO
AIO
Power
AIO
AIO
Power
AIO
Input
IO/Ipd
IO
Input
Power
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
Ipd
IN
IO/Ipu
IO/Ipd
AMDIX Enable
Pin Description
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via two resistors.
Hardware reset for the whole chip (active low)
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
3.3 V IO Power Supply.
Hard pin select enable as input (during power on reset and hardware reset) and
MII CRS as output
Full register access enable as input (during power on reset and hardware reset) and
MII COL output
AMDIX enable as input (during power on reset and hardware reset)
Receive data Bit 3 for MII
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 for MII as output.
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 for both RMII and MII
MII/SI mode select as input (during power on reset and hardware reset) and
LED # 4 as output
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 for both RMII and MII
RMII/MII select as input (during power on reset and hardware reset)
Receive data valid for MII and CRS_DV for RMII as output
10/100M input select. 1 = 100M mode, 0 = 10M mode.
TXER Input
Auto-negotiation enable(during power on reset and hardware reset)
Receive clock MII
Node/repeater select (during power on reset and hardware reset)
Receive error
Ground Connect to ground.
Ground Connect to ground.
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3
ICS1894-40
REV C 092909
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin
Number
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
Name
SPEED/
TXCLK
TXEN
TXD0
VDDD
LED3
TXD1
TXT2
TXD3
REF_OUT
REF_IN
P4/LED2
P0/LED0
P1/LED1
Pin
Type
IO/Ipu
Input
Input
Power
IO/Ipd
Input
Input
Input
Input
IO/Ipu
IO
IO
Pin Description
10M/100M select as input (during power on reset and hardware reset)
Transmit clock for MII as output
Transmit enable for both RMII and MII
Transmit data Bit 0 for both RMII and MII
Core Power Supply
LED3 output
Transmit data Bit 1for both RMII and MII
Transmit data Bit 2 for MII
Transmit data Bit 3 for MII
25 MHz crystal (or clock) input for MII. 50MHz clock input for RMII
PHY address Bit 4 as input (during power on reset and hardware reset)
And LED # 2 as output
PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Output 25 MHz crystal output
Notes:
1. Ipd = Input with internal pull-down.
Ipu = Input with internal pull-up.
Opu = Output with internal pull-up.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4
ICS1894-40
REV C 092909
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Strapping Options
Pin
Number
1
16
17
18
38
19
12
40
39
21
20
22
Pin
Name
AMDIX
HWSW/CRS
REGPIN/COL
AMDIX/RXD2
P4/LED2
P3/RXD2
P2/INT
P1/LED1
P0/LED0
SI/LED4
RXTRI/RXD1
FDPX/RXD0
Pin
Type
1
IN/Ipu
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipd
IO/
IO/
IO/Ipd
IO/Ipd
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
Pin Function
Hardware pin select enable. Active during power-on and hardware reset.
Full register access enable. Active during power-on and hardware reset.
1 = AMDIX enable
0 = AMDIX disable
The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
MII/SI mode select.
Active during power-on and hardware reset.
1=RX tri-state for MII/RMII interface
0=RX output enable
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
[1x]=RMII mode
[01]=SI mode (Serial interface mode)
[00]=MII mode
1=100M mode
0=10M mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
LED3 output
23
RMII/RXDV
IO/Ipd
24
26
27
28
SPEED
ANSEL/RXCLK
NOD/RXER
SPEED/TXCLK
IO/Ipu
IO/Ipu
IO/Ipd
IO/Ipu
32
LED3
IO/Ipu
1.
Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise.
Functional Description
The ICS1894-32 is a stream processor. During data
transmission, it accepts sequential nibbles from its MAC
(Media Access Control) converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles. It
subsequently presents these nibbles to its MAC Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
•
Physical Coding sublayer (PCS)
IDT™ / ICS™
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5
ICS1894-40
REV C 092909
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