MXED401
200-Column Cholesteric LCD Driver
FEATURES:
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Drives Reflective-type Liquid Crystal
Displays
Black-White or Gray-Scale
Cholesteric LCD (ChLCD) Compatible
200 Output Channels, Cascadeable
192-Channel Mode
Token-Based Bi-directional Data
Transfer
6-Bit Data to support 64-Level
Gray-Scale
±2V to ±7V panel drive
4mA Minimum Source/Sink at ±7VOutput
Levels
2.5V to 5V logic supply
26 MHz clock frequency
4mA Minimum Source/Sink at ±7V Output
Levels
Gold-Bumped Die @ 60 micron Output Pitch
OVERVIEW:
Clare introduces the MXED401, targeted
for the emerging non-volatile reflective LCD
market, specifically bi-stable and multi-stable
Cholesteric LCD’s. The MXED401 supports 200
phase-controlled voltage data outputs. This is
the first standard product driver for ChLCD display
panels.
FUNCTIONAL DESCRIPTION:
The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper
operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event
where each channel is a low resistive switch to external symmetric (with respect to ground) voltage
supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4)
from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning
low for the balance of the 128 CCLK cycle (before returning to its quiescent value (VSS2)). The data
driver chip is manufactured in a high voltage (30 V) CMOS process and is available in gold-bumped-
die form.
The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register.
A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal)
outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to
Left fashion. When the Temporary Register is filled its contents may be transferred to the Output
Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase
Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches
associated with each column output driver.
14580
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January 29, 2003
MXED401
FIGURE 1 - MXED401 BLOCK DIAGRAM
0197
0198 0199
00
PV4
VSS2
MV4
3
OUT0
1
CCLK
CRB
INV
6
LAT
6
D(5:0)
1
SCLK
SHR
SEL200
SRIN
REN
REG5V
01
02
3-LEVEL OUTPUT STAGE
3
3
HIN=(PV4 – 4.0V)
XIN=4.75 TO 11.0V)
3
3
3
HIN
XIN
LOGIC TO FORCE OUTPUT TO VSS2 AND HV TRANSLATOR INTERFACE
1
1
PULSE PHASE SHIFT LOGIC
6
6
OUTPUT STORAGE REGISTER (6 BITS X 200)
6
6
TEMPORARY STORAGE REGISTER (6 BITS X 200)
1
1
TOKEN BIT SHIFT REGISTER (1 BIT X 200)
1
1
1
VDD1
VSS1
SLIN
5.0 VOLT
REGULATOR
TEST
CIRCUITRY
PV4 – 4.0V
REGULATOR
HEN
HREF
6
6
6
6
6
6
1
1
1
VPCAS
RB
NON
DON
PON
VMCAS
FLYLO
FLYHI
2
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14580
MXED401
MXED401 DATA SHEET
Table of Contents
FEATURES ....................................................................................................................1
OVERVIEW ....................................................................................................................1
FUNCTIONAL DESCRIPTION .....................................................................................1
FIGURE 1 - MXED401 BLOCK DIAGRAM .................................................................2
TABLE 1 - ABSOLUTE MAXIMUM RATINGS ............................................................4
TABLE 2 - OPERATING CONDITIONS .......................................................................4
CIRCUIT DESCRIPTION ..............................................................................................5
FIGURE 2 - REGULATOR BLOCK DIAGRAM ...........................................................5
FIGURE 3 - EXAMPLE USING ON-CHIP REGULATOR ............................................5
FIGURE 4 - EXAMPLE USING EXTERNAL BIAS ......................................................5
FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS.................................................6
FIGURE 6 - HREF BLOCK DIAGRAM ........................................................................7
FIGURE 7 - EXAMPLE USING ON-CHIP HREF BIAS ...............................................7
FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS ..........................................7
FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH .....................................8
FIGURE 10 - ...................................................................................................................9
FIGURE 11 - ...................................................................................................................9
FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM ......................................... 10
FIGURE 13 THROUGH 15 - PHASE DETECTOR WAVEFORM EXAMPLES ........11
ELECTRICAL SPECIFICATIONS ........................................................................12-14
TABLE 3 - COLUMN DRIVER IC DESIGNATION TABLE ...................................... 15
TABLE 6 - AC CHARACTERISTICS ........................................................................ 16
FIGURE 16- OUTPUT WAVEFORM DEFINITION ................................................... 16
MECHANICAL SPECIFICATIONS ............................................................................ 17
DIE SPECIFICATIONS ............................................................................................... 17
FIGURE 17 - DIE DIMENSIONAL DRAWING .......................................................... 18
TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER) ................................. 19
TABLE 5 - TRUTH TABLE (DATA LATCH) .............................................................. 19
ORDERING INFORMATION ...................................................................................... 20
3
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14580
MXED401
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage VDD1
Supply voltage PV4
Supply voltage MV4
X IN i n p u t
H IN i n p u t
Logic input levels
S torage temperature
M in .
-0.3
-0.3
-9.0
-0.3
PV4-6.0
-0.3
-65
Max.
7.0
9.0
+0.3
12.0
PV4+0.3
VDD1 + 0.3
150
U n it
V
V
V
V
V
V
C e lsius
OPERATING CONDITIONS
Parameter
Supply voltage VDD1
Supply Voltage PV4
Supply Voltage MV4
H IN
X IN
Te m p e r a t u r e A m b i e n t
M in .
2.5
2
-7
PV4-4.2
4.75
-20
Max.
5.5
7
-2
PV4-3.8
11
80
V
C e lsius
U n it
V
V
V
4
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14580
MXED401
CIRCUIT DESCRIPTION
Voltage Regulator
This product may be operated from supplies as low as 2.5 Volts. The output drive transistors require
a voltage of 5.0 volts to 11.0 volts on the XIN pin to assure proper circuit operation. This bias voltage
may be developed on the chip or provided by the system designer. When XIN is provided externally,
the REN (Regulator ENable) pin is held low, and the FLYHI/FLYLO pins are left unconnected.
Systems lacking an available bias may use the on chip voltage regulator. The circuit is enabled by
forcing REN high (to VDD1). This will cause an on-chip oscillator/charge pump circuit to operate
continuously and output a somewhat regulated 5 volts at pin REG5V. A capacitor (CFLY=0.1uF) is
connected between pins FLYHI and FLYLO. A storage capacitor (CHOLD=1.0uF) is required on
REG5V. The XIN input is then connected to the REG5V output. The charge pump is capable of
driving 18 XIN loads so generally only one or two circuits are used as regulator sources. In systems
where more than one regulator circuit is enabled it is forbidden to short their respective HOLD
capacitors. Enabling the regulator causes an additional DC current of 65uA (130 uA maximum) to
flow from VDD1 to VSS1.
FIGURE 2 - REGULATOR BLOCK DIAGRAM
FIGURE 3 - EXAMPLE USING ON CHIP REGULATOR
FIGURE 4 - EXAMPLE USING EXTERNAL BIAS
5
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14580
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