MK1714-01
Spread Spectrum Multiplier Clock
Description
The MK1714-01 is a low cost, high performance clock
synthesizer with selectable multipliers and percentages
of spread spectrum designed to generate high
frequency clocks with low EMI. Using analog/digital
Phase Locked Loop (PLL) techniques, the device
accepts an inexpensive, fundamental mode, parallel
resonant crystal or clock input to produce a spread or
dithered output. This reduces the EMI amplitude peaks
at the odd harmonics by several dB. The OE pin places
both outputs into a high impedance state for board level
testing. The PD pin powers down the entire chip and
the outputs are held low.
See the MK1714-02 for other selections on input
ranges and spreads.
Features
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Packaged in 20 pin tiny SSOP
Operating voltage of 3.3V or 5V
Multiplier modes of x1, x2, x3, x4, x5, and x6
Inexpensive 10 - 25 MHz crystal or clock input
OE pin tri-states the outputs for board testing
Power down pin stops the outputs low
Selectable frequency spread
Spread can be turned on or off
Advanced, low power CMOS process
Duty cycle of 40/60
Industrial temperature range available
Available in Pb (lead) free package
Input frequency of 5 - 140 MHz (depending on mode)
Output frequency of 20 - 150 MHz (depending on
mode)
Block Diagram
V DD
2
S4:0
PD
Low EM I Enable
5
PLL Clock
M ultiplier
and Spread
Spectrum
Circuitry
C lock Out
Input
Crystal or
Clock
X1
Crystal
O scillator
X2
REF
XSEL
4
O E (both outputs)
G ND
MDS 1714-01 J
1
Revision 061305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1714-01
Spread Spectrum Multiplier Clock
Pin Assignment
X2
X1
VDD
VDD
S4
S3
GND
GND
S2
CLK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
REF
OE
PD
GND
S0
NC
S1
GND
LEE
XSEL
20 pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
X2
X1
VDD
VDD
S4
S3
GND
GND
S2
CLK
XSEL
LEE
GND
S1
NC
S0
GND
PD
OE
REF
Pin
Type
XO
XI
Power
Power
Input
Input
Power
Power
Input
Pin Description
Crystal connection. Connect to parallel mode crystal. Leave open for clock.
Crystal connection. Connect to parallel mode crystal or clock.
Connect to VDD. Must be same value as other VDD.
Connect to VDD. Must be same value as other VDD.
Select pin 4. Determines multiplier and spread amount per table on following page. Internal
pull-down.
Select pin 3. Determines multiplier and spread amount per table on following page. Internal
pull-up.
Connect to ground.
Connect to ground.
Select pin 2. Determines multiplier and spread amount per table on following page. Internal
pull-up.
Connect to VDD for crystal input, or GND for CLK input. Internal pull-down.
Low EMI Enable. Turns on spread spectrum on CLK when high. Internal pull-up.
Connect to ground.
Select pin 1. Determines multiplier and spread amount per table on following page. Internal
pull-up.
No connect. Do not connect anything to this pin.
Select pin 0. Determines multiplier and spread amount per table on following page. Internal
pull-up.
Connect to ground.
Power down. Turns off chip when low. Outputs stop low. Leave open or connected to VDD if
power down is not required.
Output enable. Tri-states all outputs when low. Internal pull-up.
Output Clock output dependent on input, multiplier, and spread amount per table on following page.
Input
Input
Power
Input
-
Input
Power
Input
Input
Output Reference clock output from crystal oscillator. This clock is not spread.
Note: When changing the input frequency, the LEE pin must be set low for minimum of 10µs to allow the PLL to lock
to the new frequency. Alternatively, the PD pin may be set low while changing frequencies.
MDS 1714-01 J
2
Revision 061305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1714-01
Spread Spectrum Multiplier Clock
Clock Output Select Table (MHz)
S4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Range
40 - 140
60 - 140
-
40 - 100
10 - 25
20 - 50
10 - 30
30 - 40
10 - 50
15 - 35
40 - 60
60 - 120
60 - 140
60 - 120
30 - 60
40 - 100
15 -25
10 - 13.33
30 - 100
30 - 80
-
5 - 20
-
10 - 17
10 - 25
8 - 20
10 - 20
10 - 15
10 - 20
8 - 16
8 - 23
8 - 16
Multiplier
x1
x1
test
x1
x2
x2
x2
x2
x3
x4
x1
x1
x1
x1
x1
x1
x4
x3
x1
x1
test
x4
test
x8
x4
x5
x6
x8
x4
x5
x6
x8
Output Range
40 - 140
60 -140
-
40 - 80
20 - 50
40 - 80
20 - 60
60 - 80
30 - 150
60 - 140
40 - 60
60 - 120
60 - 140
60 - 120
30 - 60
40 - 100
60 - 100
30 - 40
30 - 100
30 - 80
-
20 - 80
-
80 - 136
40 - 100
40 - 100
60 - 120
80 - 120
40 - 80
40 - 80
48 - 138
64 - 128
Direction
C
C
-
C
C
C
DC
DC
C
C
DC
D
DC
DC
D
DC
D
D
C
DC
-
DC
-
DC
C
C
C
C
DC
DC
DC
DC
Amount (%)
±1.25
±0.5
-
±1
±1
±0.5
+0.25, -1.25
+0.5, -1
±1
±0.5
+0.5, -1.5
-1
+0.5, -1.5
+0.5, -1.5
-2.5
+0.5, -1.5
-1
-1.5
±0.5
+0.25, -1.25
-
+0.5, -3
-
+0.5, -1
±1
±1
±1
±1
+0.25, -1.25
+0.5, -1.5
+0.5, -2
+0.5, -1.5
For S4:S0, 0 = connect to GND, 1 = connect to VDD.
Direction: C = center spread, D = down spread, DC = down + center spread. Amount = spread amount. For example, for a 40
MHz output clock spread down 1%, the lowest frequency is 39.60 MHz.
Contact ICS (ics-mk@icst.com) with your exact output frequency for details on spread direction and amount.
MDS 1714-01 J
3
Revision 061305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1714-01
Spread Spectrum Multiplier Clock
External Components
The MK1714-01 requires a minimum number of
external components for proper operation.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK1714-01.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as
possible. For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Crystal Tuning Load Capacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be
[16 - 6]*2 = 20pF.
If the output frequency is not critical, external load
capacitors are not necessary.
Powerup Considerations
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken in
the implementation of the MK1714-01.
1) An input signal should not be applied to X1 until VDD
is stable (within 10% of its final value). This
requirement can be easily met by operating the
MK1714-01 and the X1 source from the same power
supply. This requirement is not applicable if a crystal is
used.
2) LEE should not be enabled (taken high) until after
the power supplies and input clock are stable. This
requirement can be met by direct control of LEE by
system logic; for example, a “power good” signal.
Another solution is to leave LEE unconnected but place
a 0.01µF capacitor to ground. The pull-up resistor on
LEE will charge the capacitor and provide
approximately a 700µs delay until spread spectrum is
enabled.
3) If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes
at the new frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
MDS 1714-01 J
4
Revision 061305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
MK1714-01
Spread Spectrum Multiplier Clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1714-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
-0.5 to 7V
Rating
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
175°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
Max.
+85
+5.5
Units
°C
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V or 5V, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
On Chip Pull-up Resistor,
inputs
On-Chip Pull-down Resistor,
input
Input Capacitance
Symbol
VDD
IDD
IDD
V
IH
V
IL
V
OH
V
OL
I
OS
R
PU
R
PD
Conditions
No load, at 3.3V
No load, at 5V
Select inputs, OE, PD
Select inputs, OE, PD
I
OH
= -8 mA
I
OL
= 8mA
Each output
Except X1, S4
S4 pin only
Except X1, X2
Min.
3.0
Typ.
26
40
Max.
5.5
Units
V
mA
mA
V
2
0.8
VDD-0.4
0.4
±50
500
500
7
V
V
V
mA
kΩ
kΩ
pF
MDS 1714-01 J
5
Revision 061305
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
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