HY5PS56421(L)F
HY5PS56821(L)F
HY5PS561621(L)F
Revision History
Rev.
0.1
0.2
0.3
1.0
Initial Release
Editorial clean up, changed tRAS spec. for DDR2 400
1) Defined IDD Spec.
2) Added Speed bins table in AC timming specification
Transfered Functional description, command truth table pages and Some contents of
Operating conditions to <Device Operation & timing diagram>
History
Draft Date
Dec. 2003
Jan. 2004
May 2004
Jul. 2004
Rev 1.0/July. 2004
2
HY5PS56421(L)F
HY5PS56821(L)F
HY5PS561621(L)F
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default chracteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev 1.0 / July. 2004
3
HY5PS56421(L)F
HY5PS56821(L)F
HY5PS561621(L)F
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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•
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•
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•
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VDD=1.8V
VDDQ=1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe suupported (x8 only)
Self-Refresh High Temperature Entry
Ordering Information
Part No.
HY5PS56421(L)F-X*
HY5PS56821(L)F-X*
HY5PS561621(L)F-X*
Configuration Package
64Mx4
32Mx8
16Mx16
60Ball
FBGA
84Ball
FBGA
Operating Frequency
Grade
-E3
-E4
-C4
-C5
-Y5
-Y6
tCK(ns)
5
5
3.75
3.75
3
3
CL
3
4
4
5
5
6
tRCD
3
4
4
5
5
6
tRP
3
4
4
5
5
6
Unit
Clk
Clk
Clk
Clk
Clk
Clk
Note:
-X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
Rev 1.0/July. 2004
4
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