74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
March 2007
74ABT541
Octal Buffer/Line Driver with 3-STATE Outputs
Features
■
Non-inverting buffers
■
Output sink capability of 64mA, source capability of
■
■
■
■
■
■
■
■
■
tm
General Description
The ABT541 is an octal buffer and line driver with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented trans-
mitter/receiver. The ABT541 is similar to the ABT244
with broadside pinout.
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
Flow-through pinout for ease of PC board layout
Disable time less than enable time to avoid bus
contention
Ordering Information
Order Number
74ABT541CSC
74ABT541CSJ
74ABT541CMSA
74ABT541CMTC
Package
Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Inputs
Outputs
Description
Output Enable Input (Active LOW)
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
www.fairchildsemi.com
74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
Truth Table
Inputs
OE
1
L
H
X
L
OE
2
L
X
H
L
I
H
X
X
L
Outputs
H
Z
Z
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
CC
V
IN
I
IN
V
O
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage
(1)
Input
Current
(1)
Voltage Applied to Any Output
Disabled or Power-Off State
HIGH State
Current Applied to Output in LOW State (Max.)
DC Latchup Source Current
Over Voltage Latchup (I/O)
Rating
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
–0.5V to 5.5V
–0.5V to V
CC
twice the rated I
OL
(mA)
–500mA
10V
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
∆
V /
∆
t
Supply Voltage
Minimum Input Edge Rate
Data Input
Enable Input
Parameter
Free Air Ambient Temperature
Rating
–40°C to +85°C
+4.5V to +5.5V
50mV/ns
20mV/ns
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
www.fairchildsemi.com
2
74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage
Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional Outputs Enabled
I
CC
/Input Outputs 3-STATE
Outputs 3-STATE
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min.
2.0
Typ.
Max. Units
V
0.8
–1.2
V
V
V
V
0.55
1
1
7
–1
–1
µA
µA
V
10
–10
µA
µA
mA
µA
µA
µA
mA
µA
mA
mA
µA
mA/
MHz
V
µA
Min.
Min.
Min.
Max.
Max.
Max.
0.0
I
IN
=
–18mA
I
OH
=
–3mA
I
OH
=
–32mA
I
OL
=
64mA
V
IN
=
2.7V
(3)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V
(3)
V
IN
=
0.0V
I
ID
=
1.9µA, All Other Pins
Grounded
4.75
2.5
2.0
0–5.5V V
OUT
=
2.7V, OE
n
=
2.0V
0–5.5V V
OUT
=
0.5V, OE
n
=
2.0V
Max.
Max.
0.0
Max.
Max.
Max.
V
OUT
=
0.0V
V
OUT
=
V
CC
V
OUT
=
5.5V, All Others GND
All Outputs HIGH
All Outputs LOW
OE
n
=
V
CC
, All Others at V
CC
or Ground
V
I
=
V
CC
– 2.1V
Max.
Enable Input V
I
=
V
CC
– 2.1V
Data Input V
I
=
V
CC
– 2.1V,
All Others at V
CC
or Ground
Max
Outputs Open, OE
n
=
GND,
One-Bit Toggling
(2)
,
50% Duty Cycle
–100
–275
50
100
50
30
50
2.5
2.5
50
0.1
I
CCD
Dynamic I
CC
No Load
(3)
Notes:
2. For 8-bit toggling, I
CCD
<
0.8mA/MHz.
3. Guaranteed, but not tested.
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
www.fairchildsemi.com
3
74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
DC Electrical Characteristics
SOIC package.
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output
Voltage
Minimum HIGH Level Dynamic Input
Voltage
Maximum LOW Level Dynamic Input
Voltage
V
CC
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF,
R
L
=
500Ω
T
A
=
25°C
(4)
T
A
=
25°C
(4)
T
A
=
25°C
(5)
T
A
=
25°C
(6)
T
A
=
25°C
(6)
Min.
–1.3
2.7
2.0
Typ.
0.7
–0.8
3.1
1.4
1.1
Max.
1.0
Units
V
V
V
V
0.6
V
Notes:
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but
not tested.
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not
tested.
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold
(V
ILD
), 0V to threshold (V
IHD
). Guaranteed, but not tested.
AC Electrical Characteristics
SOIC and SSOP package.
T
A
=
+25°C,
V
CC
=
+5V,
C
L
=
50pF
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
T
A
=
–40°C to +85°C,
V
CC
=
4.5V–5.5V,
C
L
=
50pF
Min.
1.0
1.0
1.5
1.5
1.7
1.7
Parameter
Propagation Delay,
Data to Outputs
Output Enable Time
Min.
1.0
1.0
1.5
1.5
1.7
1.7
Typ.
2.0
2.4
3.1
3.7
3.5
3.1
Max.
3.6
3.6
6.0
6.0
6.1
5.6
Max.
3.6
3.6
6.0
6.0
6.1
5.6
Units
ns
ns
ns
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
www.fairchildsemi.com
4
74ABT541 Octal Buffer/Line Driver with 3-STATE Outputs
Extended AC Electrical Characteristics
SOIC package.
–40°C to +85°C,
V
CC
=
4.5V to 5.5V,
C
L
=
50pF,
8 Outputs
Switching
(7)
Symbol
f
TOGGLE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable
Time
T
A
=
–40°C to +85°C, T
A
=
–40°C to +85°C,
V
CC
=
4.5V to 5.5V, V
CC
=
4.5V to 5.5V,
C
L
=
250pF,
C
L
=
250pF,
1 Output
8 Outputs
(8)
Switching
Switching
(9)
Min.
Max.
Mi.n
Max.
Units
MHz
Parameter
Max Toggle
Frequency
Propagation Delay,
Data to Outputs
Output Enable Time
Min.
Typ.
100
Max.
1.5
1.5
1.5
1.5
1.0
1.0
5.0
5.0
6.5
6.5
6.1
5.6
1.5
1.5
2.5
2.5
(10)
6.0
6.0
7.5
7.5
2.5
2.5
2.5
2.5
8.5
8.5
9.5
10.5
ns
ns
ns
Notes:
7. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
8. This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors
in place of the 50pF load capacitors in the standard AC load. This specification pertains to single output switching
only.
9. This specification is guaranteed but not tested. The limits represent propagation delays for all paths described
switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load
capacitors in the standard AC load.
10. The 3-STATE delays are dominated by the RC network (500Ω, 250pF) on the output and have been excluded from
the datasheet.
©1992 Fairchild Semiconductor Corporation
74ABT541 Rev. 1.4
www.fairchildsemi.com
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
