Advanced Information
Advanced Digital Video Encoder
Y/Cb/Cr Output Support
HCMOS Technology
The MC44722A and MC44723A are advanced Digital Video
Encoders (DVE). They convert ITU-601/656 standard 4:2:2 Bit-
Paralellel data into analog composite video, S-Video or analog
component signals Y/Cb/Cr in PAL and NTSC formats. They
accept the multiplexed two 8-bit or 16-bit ((CB,Y,CR)Y) signals
from digital sources such as MPEG decoders and can act as a sync
generator master or as a sync slave. All video processing is done
digitally and requires no external adjustment.
Specifically designed for digital satellite, digital cable decoders,
multimedia terminals and DVD players.
MC44722A
MC44723A
Freescale Semiconductor, nc...
I
FT SUFFIX
48 QFP
(0.8mm Pitch)
• World Wide Operation (PAL-BDGHI, PAL-N,PAL-M, NTSC-M)
• SMPTE 170M / ITU - R 624 composite video output
• Programmable Color Sub-carrier Frequencies
VFU SUFFIX
48 VQFP
• Analog standard timing for Horizontal, Vertical, Frame and
(0.5mm Pitch)
Composite Sync Outputs
• Sync Extraction From Digital Input Data (SAV, EAV)
• Sync Polarity and Horizontal / Vertical Phase Control
• Master or Slave Sync (H/Vsync, H/Fsync, ITU-R656 Slave) Operation
• Interlaced or Non-Interlaced Support
• 625/50 or 525/60 ITU-601/656 two 8-bit or 16-bit ((CB,Y,CR)Y) Digital Input
• Luma 2X / Chroma 4X Output interpolating Filter
• Dual Digital A / B selectable inputs
• External VBI Information Data Input (Teletext Information Data)
• Selectable One set of Signal within (CVBS/Y/C) or (Y/Cb/Cr)
• Selectable Analog Component Output ( Beta Cam or MII Component Interface Level )
• Three Analog Outputs Through 10-bit DACs
• Easily programmed via Serial Bus ( I2C or 4-Wired SPI Bus)
• 2 Hardware selectable I2C Chip Addresses
• Closed-Caption, CGMS and WSS Information data Insertion
• MACROVISION ver. 7.01 Anti-Copy Signal Insertion(MC44722A Only)
• On Chip Color - bar Generator
• 5V Tolerante Input
• +3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply
• Pin Compatible with MC44722/3
The MC44722A device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098
and other intellectual property rights. The use of Macrovision's copy protection technology in
the device must be authorized by Macrovision and is intended for home and other limited pay-
per-view uses only, unless otherwise authorized in writing by Macrovision.
Reverse engineering or disassembly is prohibited.
No. 1
For More Information On This Product,
MC44722A/3A Rev 0.05 07/15/98
Go
Specifications and information herein are subject
This document contains information on a new product.
to: www.freescale.com
to change without notice.
Freescale Semiconductor, Inc.
[Pin Assignment]
46
45
39
44
38
DVIB7
43
48
42
47
41
Freescale Semiconductor, Inc...
DVIB1
DVdd
DVss
DVIB4
DVIB6
40
1
2
3
4
5
6
7
8
9
10
11
12
CVBS / Cb
CVBS / Cb
CVBS/CbVdd
Y
Y
YVdd
C / Cr
C / Cr
CVdd
DAVss
Ibias
PAL/NTSC
DAVdd
ChipA
SCL/SCK
SDA/SI
VReff
TEST
DVdd
DVss
clock
Reset
SEL
A/B_sel
Hsync
F / Vsync
C/Fsync/VBI
Vmute
DVIA0
DVIB0
DVIB2
DVIB3
DVIB6
TP
37
36
35
34
33
32
31
30
29
28
27
26
25
MC44722A
MC44723A
DVIA1
DVIA2
DVIA3
DVIA4
DVIA5
DVIA6
DVIA7
16
SO
17
23
18
13
19
14
20
15
21
No. 2
For More Information On This Product,
MC44722A/3A Rev 0.05 07/15/98
Go to: www.freescale.com
This document contains information on a new product. Specifications and information herein are subject to change without notice.
22
24
Freescale Semiconductor, Inc.
[Pin Descriptions]
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25~32
33
34
35
36
37
38~41
42
43
44~47
48
NAME
I/O
DESCRIPTIONS
Analog composite video signal output or Cb signal output current drive(positive)
Analog composite video signal output or Cb signal output current drive(negative)
Power Supply for CVBS / Cb DAC circuit
Analog luminance signal output current drive(positive)
Analog luminance signal output current drive(negative)
Power Supply for Y DAC circuit
Analog chrominance signal output or Cr signal output current drive(positive)
Analog chrominance signal output or Cr signal output current drive(negative)
Power Supply for C / Cr DAC circuit
Ground for DAC circuit
Reference current for the 3 DACs
Power Supply for DAC circuit
Reference full scale voltage for the 3 DACs
I2C chip address select { 0 : 42(hex)/43(hex) 1 : 1C(hex )/1D(hex) }
TEST pin(Ground)
If SPI mode, serial data output / If I2C mode, connect to Ground
Serial data input, Open drain output / If SPI mode, serial data input
Serial clock
Connect to Ground / If SPI mode, this pin is chip select
Ground for Digital circuit
27MHz clock input
Power Supply for Digital circuit
Reset signal, active LOW
NTSC/PAL select . This pin active only Reset time. (NTSC : Low PAL : High )
8-bit Multiplexed Y/Cr/Cb 4:2:2 data(ITU Rec656) input(DVIA) or Multiplexed Y data
(ITU- Rec656/601) input in 16-bit input mode (DVIA7 : MSB )
Video mute on Reset ( 0 : nomal, 1 : mute ), or TEST data input
Csync/Frame sync output or external VBI information input
Frame sync or Vertical sync input/output
Horizontal sync input/output
Switch control for 8-bit X 2 Multiplexed Y/Cr/Cb 4:2:2 data(ITU- Rec656) input
(DVIA) or (DVIB) , or test data I/O
8-bit Multiplexed 4:2:2 data(ITU- Rec656/601) input(2), or Multiplexed Cr/Cb data
(ITU- Rec656/601) input in 16-bit input mode (MSB: DVIB8), or Test data input/output
Ground for Digital circuit
Power Supply for Digital circuit
8-bit Multiplexed 4:2:2 data(ITU- Rec656/601) input(DVIB), or Multiplexed Cr/Cb
data(ITU- Rec656/601) input in 16-bit input mode (LSB:DVIB1), or Test data I/O
for test (should be ground)
Freescale Semiconductor, Inc...
CVBS / Cb
O
CVBS /Cb
O
CVBS/CbVdd
Y
O
Y
O
YVdd
C/Cr
O
C/Cr
O
C/CrVdd
DAVss
Ibias
O
DAVdd
VReff
ChipA
TEST
I
SO
z(O)
SDA/SI
I/O(I)
SCL/SCK
I
SEL
(I)
DVss
CLOCK
I
DVdd
Reset
I
PAL/NTSC
I
DVIA7~0
I
Vmute
C/Fsync/VBI
F/Vsync
Hsync
A/B_sel
DVIB8~5
DVss
DVdd
DVIB4~1
TP
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note : Power Supply Group
Digital ---> 22-pin, 43-pin,
Analog ---> 3-pin, 6-pin, 9-pin, 12-pin
No.
3
For More Information On This Product,
MC44722A/3A Rev 0.05 07/15/98
Go to: www.freescale.com
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Freescale Semiconductor, Inc.
[Block Diagram]
C/Fsync/VBI
F/Vsync
Hsync
YVdd
DVdd
DVdd
DVss
DVss
0
CGMS_gen
CC_gen
Freescale Semiconductor, Inc...
Sync_generator
BG
copy
protection
bus
CVBS/CbVdd
C/CrVdd
DAC
YOUT
YOUT
CVBSOUT / Cb
CVBSOUT / Cb
COUT / Cr
COUT / Cr
VReff
Ibias
DAVdd
H,V
0
demux
Cb
Cr
0
0
subcarrier
gen
DVIB[7 : 0]
Vmute
TP
clock
ChipA
Reset
PAL/NTSC
0
0
Modulator
I2C / SPI
TEST
BIAS
DAC
DAC
DVIA[7 : 0]
Y
0
off_set
MC44722A/3A
SDA/SI
SCL/SCK
SEL
SO
TEST
DAVss
I2C/SPI chip-address
42/43(hex)
1C/1D(hex)
No. 4
For More Information On This Product,
MC44722A/3A Rev 0.05 07/15/98
Go to: www.freescale.com
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Freescale Semiconductor, Inc.
[Function Descriptions]
Clock
27.0MHz. This signal on the clock pin needs to be active and stable for 5 cycles before the reset pin is
de-asserted.
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE
clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/
NTSC, Vmute and SEL pins.
The PAL/NTSC pin determines the default values for the DVE control registers. The default register
values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately
when a valid input digital video data stream is present and Vmute is Low at reset.
The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the
video output is muted - output signal is "black - sync". When "0" at reset, the video output is from the
input video data. This control can be used to mute the disable noise signals from a MPEG decoder at reset
until a clear and stable picture is available.
The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus
operation. If High, the DVE use 4-wired SPI operation.
After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled.
(see page --- for sub-address register descriptions.)
Freescale Semiconductor, Inc...
Fig 1 : DVIA/DVIB Data Input Timing
Input Clock 27MHz
50%
Tds
Input Data
DVIA/DVIB
Tdh
Fig 2 : Sync Data Output Timing
Clock 27MHz
Output Data
TP
Output data
H/V/F sync
Td
Td
No. 5
For More Information On This Product,
MC44722A/3A Rev 0.05 07/15/98
Go to: www.freescale.com
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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