PD -
96171
IRFB4615PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
TO-220AB
IRFB4615PbF
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D
150V
32m
:
39m
:
35A
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
35
25
140
144
0.96
± 20
38
-55 to + 175
300
10lb in (1.1N m)
109
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
c
e
°C
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
f
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient (PCB Mount)
j
Parameter
Typ.
Max.
1.045
Units
°C/W
ij
–––
0.50
–––
62
www.irf.com
1
09/05/08
IRFB4615PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G(int)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
150
–––
–––
3.0
–––
–––
–––
–––
–––
Conditions
–––
0.19
32
–––
–––
–––
–––
–––
2.7
–––
V V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 5mA
39
mΩ V
GS
= 10V, I
D
= 21A
5.0
V V
DS
= V
GS
, I
D
= 100µA
V
DS
= 150V, V
GS
= 0V
20
µA
250
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
100
V
GS
= 20V
nA
V
GS
= -20V
-100
f
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
35
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
26
8.6
9.0
17
15
35
25
20
1750
155
40
179
382
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
Conditions
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
hÃ
V
DS
= 50V, I
D
= 21A
I
D
= 21A
V
DS
= 75V
nC
V
GS
= 10V
I
D
= 21A, V
DS
=0V, V
GS
= 10V
V
DD
= 98V
I
D
= 21A
ns
R
G
= 7.3Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
(See Fig.5)
pF ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 120V (See Fig.11)
V
GS
= 0V, V
DS
= 0V to 120V
f
f
h
g
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Min. Typ. Max. Units
–––
–––
–––
–––
35
A
140
Conditions
MOSFET symbol
showing the
integral reverse
G
S
D
Ã
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
––– –––
1.3
V
–––
70
–––
ns
–––
83
–––
––– 177 –––
nC
T
J
= 125°C
––– 247 –––
–––
4.9
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 21A, V
GS
= 0V
V
R
= 100V,
T
J
= 25°C
T
J
= 125°C
I
F
= 21A
di/dt = 100A/µs
T
J
= 25°C
f
f
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.51mH
R
G
= 25Ω, I
AS
= 21A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
21A, di/dt
≤
549A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application
note #AN-994
R
θ
is measured at T
J
approximately 90°C
2
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IRFB4615PbF
1000
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
1000
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
100
BOTTOM
10
BOTTOM
10
5.0V
1
1
5.0V
≤
60µs PULSE WIDTH
Tj = 25°C
0.01
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
0.1
≤
60µs PULSE WIDTH
Tj = 175°C
0.1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 2.
Typical Output Characteristics
3.0
ID = 21A
VGS = 10V
ID, Drain-to-Source Current (A)
100
2.5
TJ = 175°C
TJ = 25°C
2.0
10
1.5
1
VDS = 50V
≤60µs
PULSE WIDTH
0.1
2
4
6
8
10
12
14
16
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Fig 4.
Normalized On-Resistance vs. Temperature
14.0
VGS, Gate-to-Source Voltage (V)
12.0
10.0
8.0
6.0
4.0
2.0
0.0
ID= 21A
VDS= 120V
VDS= 75V
VDS= 30V
10000
C, Capacitance (pF)
Ciss
1000
Coss
Crss
100
10
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0
5
10
15
20
25
30
35
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4615PbF
1000
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100µsec
1msec
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
T J = 175°C
10
T J = 25°C
10
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
100
1000
VGS = 0V
1.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
40
35
30
25
20
15
10
5
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8.
Maximum Safe Operating Area
190
185
180
175
170
165
160
155
150
145
140
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
Id = 5mA
ID, Drain Current (A)
Fig 9.
Maximum Drain Current vs.
Case Temperature
3.0
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10.
Drain-to-Source Breakdown Voltage
500
450
400
350
300
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
ID
TOP
2.8A
5.3A
BOTTOM 21A
2.5
2.0
Energy (µJ)
1.5
1.0
0.5
0.0
-20
0
20
40
60
80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRFB4615PbF
10
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
R
3
R
3
τ
3
R
4
R
4
τ
C
τ
τ
1
τ
2
τ
3
τ
4
τ
4
Ri (°C/W)
0.02324
0.26212
0.50102
0.25880
τi
(sec)
0.000008
0.000106
0.001115
0.005407
0.01
SINGLE PULSE
( THERMAL RESPONSE )
1E-005
0.0001
Ci=
τi/Ri
Ci i/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
0.001
1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj
= 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
10
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 21A
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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EAR , Avalanche Energy (mJ)
5
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