Preliminary
GS818QV18/36D-200/167/133
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual DoubleData Rate interface
• Echo Clock outputs track data output drivers
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
18Mb
Σ
2x2B2V
SigmaQuad SRAM
133 MHz–200 MHz
2.5 V V
DD
1.8 V and 1.5 V I/O
Bottom View
-200
tKHKH
tKHQV
5.0 ns
2.3 ns
-167
6.0 ns
2.5 ns
-133
7.5 ns
3.0 ns
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
SigmaRAM™ Family Overview
GS818QV18/36 are built in compliance with the SigmaQuad SRAM
pinout standard for Separate I/O synchronous SRAMs. They
are18,874,368-bit (18Mb) SRAMs. These are the first in a family of
wide, very low voltage HSTL I/O SRAMs designed to operate at the
speeds needed to implement economical high performance
networking systems.
SigmaQuad SRAMs are offered in a number of configurations. Some
emulate and enhance other synchronous separate I/O SRAMs. A
higher performance SDR (Single Data Rate) Burst of 2 versionis also
offered. The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of address
bursting, output data registering, and write cueing. Along with the
Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs
allows a user to implement the interface protocol best suited to the
task at hand.
input register clock inputs, K and K. K and K are independent single-
ended clock inputs, not differential inputs to a single differential clock
input buffer. The device also allows the user to manipulate the output
register clock inputs quasi independently with the C and C clock
inputs. C and C are also independent single-ended clock inputs, not
differential inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead. Each
Σ
2x2B2 igmaQuad
SRAM also supplies Echo Clock outputs, CQ and CQ, that are
synchronized with read data output. When used in a source
synchronous clocking scheme, these Echo Clock outputs can be used
to fire input registers at the data’s destination.
Clocking and Addressing Schemes
A
Σ
2x2B2SigmaQuad SRAM is a synchronous device. It employs two
Because Separate I/O
Σ
2x2B2 RAMs always transfer data in two
packets, A0 is internally set to 0 for the first read or write transfer, and
automatically incremented by 1 for the next transfer. Because the LSB
is tied off internally, the address field of a
Σ
2x2B2 RAM is always one
address pin less than the advertised index depth (e.g., the 1M x 18
has a 512K addressable index).
Rev: 1.01 11/2002
1/29
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS818QV18/36D-200/167/133
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW1
BW0–BW3
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
MCL
CQ
CQ
Q0–Q35
D0–D17
Q0–Q17
V
DD
V
DDQ
V
SS
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Synchronous Byte Writes
Input Clock
Input Clock
Output Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Synchronous Echo Clock Output
Synchronous Echo Clock-bar Output
Synchronous Data Outputs
Synchronous Data Inputs
Synchronous Data Outputs
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Output
Output
Output
Input
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active Low
Active Low
x18 Version
Active Low
x36 Version
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
Echoes C or K Clock
Echoes C or K Clock
x36 Version
x18 Version
x18 Version
2.5 V Nominal
1.5 V Nominal
—
Note: NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
Rev: 1.01 11/2002
4/29
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS818QV18/36D-200/167/133
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that
shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from
differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application
at hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM but does not disable the CQ or CQ output pins.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.
Rev: 1.01 11/2002
5/29
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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