VHD6 Series 3.3V
VCXO CMOS Oscillator
December 2008
• Pletronics’ VHD6 Series is a voltage controlled
crystal oscillator with a CMOS output.
• This model uses fundamental mode crystals
with no multiplication circuits.
• Tape and Reel or tube packaging is available.
•
•
•
•
10 to 108 MHZ
3.2 x 5 mm Ceramic LCC Package
Voltage Control Function on pad 1
Enable/ Disable Function on pad 2
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.09 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
CC
Supply Voltage
Vi
Vo
Input Voltage
Output Voltage
Unit
-0.5V to +5.5V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
Thermal Characteristics
The maximum die or junction temperature is 155
o
C
The thermal resistance junction to board is 60 to 100
o
C/Watt depending on the solder pads, ground plane
and construction of the PCB.
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2008, Pletronics Inc.
VHD6 Series 3.3V
VCXO CMOS Oscillator
December 2008
Part Number:
VHD6031035
E
G
500
100
-16.384M
-XX
Internal code or blank
Nominal Frequency in MHZ
Pullability in ppm (Vcontrol)
050
= _ 50 ppm minimum
+
100
= _ 100 ppm minimum
+
Stability in ppm
000
= APR
250
= _ 25 ppm
+
500
= _ 50 ppm
+
Highest Specified Operating Temperature
A
= +40
o
C
F
= +65
o
C
L
= +90
o
C
B
= +45
o
C
G
= +70
o
C
M
= +95
o
C
C
= +50
o
C
H
= +75
o
C
N
= +100
o
C
P
= +105
o
C
D
= +55
o
C
J
= +80
o
C
o
o
E
= +60 C
K
= +85 C
Lowest Specified Operating Temperature
J
= -30
o
C
A
= +10
o
C
E
= -10
o
C
o
o
F
= -15 C
K
= -35
o
C
B
= +5 C
G
= -20
o
C
L
= -40
o
C
C
= +0
o
C
H
= -25
o
C
M
= -45
o
C
D
= -5
o
C
Series (Part Type, Logic & Package)
Part Marking:
PLE VHD6
FF.FFFM
C
YMDXX
Legend:
P or PLE
FF.FFFM
YMD
xx
= Pletronics
= Frequency in MHZ
= Date of Manufacture
= Internal factory codes
Specifications such as frequency stability, supply voltage and operating temperature range, etc. are not
identified from the marking. External packaging labels and packing list will correctly identify the ordered
Pletronics part number.
Codes for Date Code YMD
Code
Year
Code
Month
Code
Day
Code
Day
Code
Day
1
1
D
13
T
25
8
2008
A
JAN
2
2
E
14
U
26
9
2009
B
FEB
0
2010
C
MAR
3
3
F
15
V
27
1
2011
D
APR
4
4
G
16
W
28
E
MAY
5
5
H
17
X
29
2
2012
F
JUN
6
6
J
18
Y
30
3
2013
G
JUL
7
7
K
19
Z
31
H
AUG
8
8
L
20
4
2014
J
SEP
9
9
M
21
K
OCT
A
10
N
22
L
NOV
B
11
P
23
M
DEC
C
12
R
24
www.pletronics.com
425-776-1880
2
VHD6 Series 3.3V
VCXO CMOS Oscillator
December 2008
Electrical Specification for 3.30V _5% over the specified temperature range
+
Item
Frequency Range
Frequency Accuracy
1
Pullability
1
Min
10
_ 25
+
_
+90
Typ
-
-
-
Max
108
-
+125
_
Unit
MHZ
ppm
ppm
Not specified if APR is specified
For Vcontrol 1.65 V _ 1.5 V.
+
Not specified if APR is specified
Defined by the part number
Absolute Pull Range, includes the effect of
temperature stability
Defined by the part number
Condition
Pullability (APR)
1
_ 50
+
-
-
ppm
Output Waveform
Output High Level
Output Low Level
Output T
RISE
and T
FALL
Output Symmetry
Vcontrol Resistance Pin 1
Modulation Bandwidth
Integrated Jitter
E/D Internal Pull-up
V disable
V enable
Output leakage
V
OUT
= V
CC
V
OUT
= 0V
Enable time
Disable time
Start up time
Supply Current
Operating Temperature
Storage Temperature Range
90
-
-
45
20
10
-
50
-
85
-10
-10
-
-
-
-
-45
-55
-
-
CMOS
-
10
6.0
55
-
-
0.6
-
15
-
+10
+10
250
250
10
8.0
+105
+125
%
%
nS
%
Kohm
KHz
pS
Kohm
%
%
uA
uA
nS
nS
mS
mA
o
of V
CC
for I
OH
= +7 mA
of V
CC
for I
OL
= -7 mA
10% to 90% of V
CC
, C
LOAD
= 15 pF
at 50% point of V
CC
(See load circuit)
3.0
50
25
20
0.4
-
-
-
-
-
-
-
1.5
5.0
Vcontrol = 1.65V +1.65V, -3dB
_
12 KHz to 20 MHZ
to V
CC
of V
CC
applied to pin 1
of V
CC
applied to pin 1
Pin 1 low, device disabled
Time for output to reach a logic state
Time for output to reach a high Z state
Time for output to reach specified frequency
C
LOAD
= 15 pF
Defined by part number
C
C
o
Specifications with Pad 2 E/D open circuit
1
For all supply voltages, load changes, aging for 1 year, shock, vibration and temperatures.
www.pletronics.com
425-776-1880
3
VHD6 Series 3.3V
VCXO CMOS Oscillator
December 2008
Load Circuit and Test Waveform
Symmetry
Vhigh
90% * Vcc
50% * Vcc
10% * Vcc
Vlow
Ground
Trise
Tfall
Reliability
: Environmental Compliance
Parameter
Mechanical Shock
Vibration
Solderability
Thermal Shock
Condition
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Human Body Model
Charged Device Model
Minimum Voltage
1500
1000
Conditions
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Bar code is 39-Full ASCII
(example actual PN will appear)
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
www.pletronics.com
425-776-1880
4
VHD6 Series 3.3V
VCXO CMOS Oscillator
December 2008
Mechanical:
Inches
A
B
C
D
1
E
1
0.197 +0.006
_
0.125 +0.006
_
0.053 max
0.050
0.050
0.004
0.039
0.025
0.020
0.004R
0.008R
mm
5.00 +0.15
_
3.20 +0.15
_
1.35 max
1.27
1.27
0.10
1.00
0.63
0.50
0.10R
0.20R
1
1
2
6
5
3
4
F
1
G
1
H
1
I
1
Contacts
:
Gold 11.8 µinches 0.3 µm minimum over
Nickel 50 to 350 µinches 1.27 to 8.89 µm
1
Typical dimensions
J
1
K
1
Not to Scale
Pad
1
2
Function
Vcontrol Input
Output
Enable/ Disable
Ground (GND)
Output
N.C.
Supply Voltage
(V
CC
)
Note
When this pad is not connected, the oscillator shall operate
When this pad is logic low, the output will be inhibited (high impedance state)
Recommend connecting this pad to V
cc
if the oscillator is to be always on
3
4
5
6
No Internal connection, pad may be connected to ground or V
CC
Recommend connecting appropriate power supply bypass capacitors as close as
possible.
Layout and application information
For Optimum Jitter Performance, Pletronics recommends:
•
a ground plane under the device
•
no large transient signals (both current and voltage) should be routed under the device do not layout
near a large magnetic field such as a high frequency switching power supply
•
do not place near piezoelectric buzzers or mechanical fans.
www.pletronics.com
425-776-1880
5
PCB设计
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