Document Revision History
Version History
Rev 0.0
Rev 1.0
Initial release
Fixed typos in Section 1.1.3; Replace any reference to Flash Interface Unit with Flash
Memory Module; added note to Vcap pin in
Table 2-2;
corrected
Table 4-4,
removed
unneccessary notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added
ADC calibration information to
Table 10-23
and new graphs in
Figure 10-22
Corrected 2.2μF to 0.1
μF
low ESR capacitor in
Table 2-2.
Replaced
Table 10-16
with
correct parameters for the 128 package pinout. Corrected (fout/2) with (fout) in
Table 10-14.
Corrected pinout labels in
Figure 11-1.
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and
other Program Flash modes, clarification to
Table 10-22,
corrected Digital Input Current Low
(pullup enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Correcting
Table 4-6
Address locations.
Added 56F8155 information; edited to indicate differences in 56F8355 and 56F8155. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout the family. Clarified I/O power
description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Updated
Table 10-23
to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial)
in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference
crystal frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
Corrected bootflash memory map layout in
Table 4-4
to 16KB.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a
debugging environment, TRST may be tied to V
SS
through a 1K resistor.
Description of Change
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev. 12
Please see http://www.freescale.com for the most current data sheet revision.
56F8355 Technical Data, Rev. 17
2
Freescale Semiconductor
Preliminary
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MC56F8357VVFE in 160 MAPBGA packages
Document Revision History (Continued)
Version History
Rev 13
Description of Change
•
Table 2-2
— TDO pullup is not enabled
•
Table 2-2
— PWM pullup is not enabled
•
Table 2-2
— CAN_TX — remove pullup related text
•
Table 2-2
— Adding pullup is enabled to several rows for clarification
•
Section 4
— Factory Programmed Memory — add ADC callibration vector
Rev 14
•
Section 4
— Factory Programmed Memory — remove ADC callibration vector
•
Section 10
— Add
Figure 10-1
•
Section 10
— ADC correction factor refinement in
Table 10-23
Rev 15
Rev 16
•
Table 2-2
— Remove pullup is enabled from TDO, PWMA0–PWMA5, and
PWMB0–PWMB5.
•
Figure 10-1
— Label the vertical axis and include the phrase “maximum current” in the
title of the figure.
• Remove the equation fragment from the bottom of
Table 10-3 on page 133.
Rev 17
•
Table 10-23
— Added non-averaged DC drift of error over temperature specification and
footnote.
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MC56F8357VVFE in 160 MAPBGA packages
56F8355/56F8155 General Description
Note:
Features in italics are NOT available in the 56F8155 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 256KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 16KB Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
RSTO
RESET
6
3
4
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or
GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
Program Controller
and Hardware
Looping Unit
• Up to two Quadrature Decoders
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
AD1
VREF
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
Boot ROM
8K x 16 Flash
Data Memory
4K x 16 Flash
8K x 16 RAM
AD0
AD1
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
*
External
Address Bus
Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
Temp_Sense
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad Timer C
or GPIOE
Quad Timer D
or
GPIOE
FlexCAN
System Bus
Control
*
External
Data
Bus Switch
*
Bus
Control
4
D7-10 or GPIOF0-3
6
IPBus Bridge (IPBB)
Peripheral
Device Selects
GPIOD0-5 or CS2-7
4
2
4
2
Decoding
Peripherals
RW
Control
IPAB
IPWDB
IPRDB
*
EMI not functional in
this package; use as
GPIO pins
Clock
resets
PLL
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8355/56F8155 Block Diagram
56F8355 Technical Data, Rev. 17
4
Freescale Semiconductor
Preliminary
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MC56F8357VVFE in 160 MAPBGA packages
External Bus
Interface Unit
Table of Contents
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
1.4
1.5
1.6
2.1
2.2
3.1
3.2
3.3
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7.1
7.2
56F8355/56F8155 Features . . . . . . . . . . . 6
Device Description . . . . . . . . . . . . . . . . . . 8
Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . 10
Architecture Block Diagram . . . . . . . . . . 10
Product Documentation . . . . . . . . . . . . . 14
Data Sheet Conventions. . . . . . . . . . . . . 15
Introduction . . . . . . . . . . . . . . . . . . . . . . . 16
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction . . . . . . . . . . . . . . . . . . . . . . . 35
External Clock Operation . . . . . . . . . . . . 35
Registers. . . . . . . . . . . . . . . . . . . . . . . . . 37
Introduction . . . . . . . . . . . . . . . . . . . . . . . 37
Program Map . . . . . . . . . . . . . . . . . . . . . 38
Interrupt Vector Table . . . . . . . . . . . . . . . 40
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 43
Flash Memory Map . . . . . . . . . . . . . . . . . 43
EOnCE Memory Map . . . . . . . . . . . . . . . 44
Peripheral Memory Mapped Registers . . 45
Factory Programmed Memory . . . . . . . . 72
Introduction . . . . . . . . . . . . . . . . . . . . . . . 72
Features . . . . . . . . . . . . . . . . . . . . . . . . . 73
Functional Description . . . . . . . . . . . . . . 73
Block Diagram . . . . . . . . . . . . . . . . . . . . 75
Operating Modes . . . . . . . . . . . . . . . . . . 75
Register Descriptions . . . . . . . . . . . . . . . 76
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Overview. . . . . . . . . . . . . . . . . . . . . . . . 104
Features . . . . . . . . . . . . . . . . . . . . . . . . 104
Operating Modes . . . . . . . . . . . . . . . . . 104
Operating Mode Register . . . . . . . . . . . 105
Register Descriptions . . . . . . . . . . . . . . 106
Clock Generation Overview . . . . . . . . . 120
Power Down Modes Overview . . . . . . . 120
Stop and Wait Mode Disable Function . 121
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 122
Operation with Security Enabled . . . . . 122
Flash Access Blocking Mechanisms. . . 123
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 125
8.1
8.2
8.3
9.1
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
11.1
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . 125
Memory Maps . . . . . . . . . . . . . . . . . . . . 126
Configuration . . . . . . . . . . . . . . . . . . . . 126
56F8355 Information. . . . . . . . . . . . . . . 131
General Characteristics . . . . . . . . . . . . 131
DC Electrical Characteristics . . . . . . . . 135
AC Electrical Characteristics . . . . . . . . 139
Flash Memory Characteristics . . . . . . . 140
External Clock Operation Timing . . . . . 140
Phase Locked Loop Timing . . . . . . . . . 141
Crystal Oscillator Timing . . . . . . . . . . . . 141
Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 142
Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . . . . 144
Quad Timer Timing . . . . . . . . . . . . . . . . 147
Quadrature Decoder Timing . . . . . . . . . 148
Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 149
Controller Area Network (CAN) Timing. 149
JTAG Timing. . . . . . . . . . . . . . . . . . . . . 150
Analog-to-Digital Converter (ADC)
Parameters. . . . . . . . . . . . . . . . . . 151
Equivalent Circuit for ADC Inputs . . . . . 155
Power Consumption . . . . . . . . . . . . . . . 155
56F8355 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 157
56F8155 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 160
Thermal Design Considerations . . . . . . 165
Electrical Design Considerations . . . . . 166
Power Distribution and I/O Ring
Implementation167
Part 9 Joint Test Action Group (JTAG) 131
Part 10Specifications . . . . . . . . . . . . . . . 131
Part 2 Signal/Connection Descriptions. 16
Part 3 On-Chip Clock Synthesis (OCCS) 35
Part 4 Memory Map . . . . . . . . . . . . . . . . . 37
Part 5 Interrupt Controller (ITCN) . . . . . 72
Part 11Packaging . . . . . . . . . . . . . . . . . . 157
Part 6 System Integration Module (SIM)104
12.1
12.2
12.3
Part 12Design Considerations . . . . . . . 165
Part 13Ordering Information . . . . . . . . . 168
Part 7 Security Features. . . . . . . . . . . . 122
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MC56F8357VVFE in 160 MAPBGA packages
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