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IS61NLP409618B-166M3L: 产品描述ZBT SRAM, 4MX18, 3.5ns, CMOS, PBGA165, LFBGA-165; 产品类别存储存储; 文件大小1MB，共39页; 制造商Integrated Silicon Solution ( ISSI ); 标准

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IS61NLP409618B-166M3L概述

ZBT SRAM, 4MX18, 3.5ns, CMOS, PBGA165, LFBGA-165

IS61NLP409618B-166M3L规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Integrated Silicon Solution ( ISSI )
零件包装代码	BGA
包装说明	LBGA,
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	3.5 ns
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	17 mm
内存密度	75497472 bit
内存集成电路类型	ZBT SRAM
内存宽度	18
湿度敏感等级	3
功能数量	1
端子数量	165
字数	4194304 words
字数代码	4000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	4MX18
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
座面最大高度	1.4 mm
最大供电电压 (Vsup)	3.465 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	10
宽度	15 mm
Base Number Matches	1

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IS61NLP204836B/IS61NVP/NVVP204836B

IS61NLP409618B/IS61NVP/NVVP409618B

2M x 36 and 4M x 18

72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control us-

ing MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

NLP: V

3.3V (± 5%), V

ddq

3.3V/2.5V (± 5%)

NVP: V

2.5V (± 5%), V

ddq

2.5V (± 5%)

NVVP: V

1.8V (± 5%), V

ddq

1.8V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

ADVANCED INFORMATION

FEBRUARY 2013

DESCRIPTION

The 72 Meg product family features high-speed, low-power

synchronous static RAMs designed to provide a burstable,

high-performance, 'no wait' state, device for networking

and communications applications. They are organized as

2,096,952 words by 36 bits and 4,193,904 words by 18

bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the ADV

input. When the ADV is HIGH the internal burst counter

is incremented. New external addresses can be loaded

when ADV is LOW.

Write cycles are internally self-timed and are initiated

by the rising edge of the clock inputs and when

LOW. Separate byte enables allow individual bytes to be

written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-250

2.6

250

-200

3.1

200

166

3.5

166

Units

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00C

02/20/2013