Table 3. Operating Conditions for CY2308AZC–XX Commercial Temperature Devices
Parameter
V
DD
T
A
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Input Capacitance
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
Description
Min.
3.135
0
Max.
3.465
70
7
500
Unit
V
°C
pF
ms
Table 4. Electrical Characteristics for CY2308AZC–XX Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
I
OL
I
OH
I
DDS
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW
(–1H)
Output HIGH Current
[3]
(–1, –2) V
OH
= V
DD
– 0.5V
(–1H)
Power-down Supply Current
Supply Current
REF = 0V, S1 = V
DD
, S2 = V
DD
Unloaded outputs @ 200 MHz
Loaded outputs @ 200 MHz, C
L
= 10 pF
Table 5. Switching Characteristics for CY2308AZC–XX Commercial Temperature Devices
[4]
Parameter
Name
Reference Frequency
Reference Edge Rate
Reference Duty Cycle
t
1
Output Frequency
Duty Cycle
[3]
= t
2
÷
t
1
t
3
t
4
t
TB
Rising Edge Rate
Falling Edge
[3]
(–1H)
Test Conditions
CMOS Levels, 30% of V
DD
CMOS Levels, 70% of V
DD
V
IN
= 0V
V
IN
= V
DD
–2) V
OL
= 0.5V
Min.
0.7
Max.
0.25
50.0
10.0
Unit
V
DD
V
DD
µA
µA
mA
Current
[3]
(–1,
12
18
–12
–18
50
115
145
mA
µA
mA
Test Conditions
30% to 70% of V
DD
C
L
= 10 pF
C
L
= 15 pF
Measured at V
DD
/2
20% to 80% of V
DD
, C
L
= 15 pF
80% to 20% of V
DD
, C
L
= 15 pF
80% to 20% of V
DD
, C
L
= 15 pF
Min.
50
0.5
25
50
50
45.0
0.8
1
0.8
1
Typ.
Max.
200
4
75
200
140
Unit
MHz
V/ns
%
MHz
MHz
%
V/ns
V/ns
V/ns
V/ns
ps
50.0
55.0
4
4
4
4
650
850
Rising Edge Rate
[3]
(–1, –2) 20% to 80% of V
DD
, C
L
= 15 pF
Falling Edge Rate
[3]
(–1, –2)
Rate
[3]
(–1H)
TTB window, Bank A and B Outputs @ 200 MHz, Tracking Skew Not
Same Frequency
[5]
Included
TTB window, Bank A and B
Different Frequency
[5]
Notes:
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters are specified with loaded outputs.
5. t
TB
is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-
cycle jitter, and dynamic phase error. t
TB
will be equal to or smaller than the maximum specified value at a given output frequency.
Document #: 38-07377 Rev. *C
Page 3 of 8
CY2308A
Table 5. Switching Characteristics for CY2308AZC–XX Commercial Temperature Devices
[4]
(continued)
Parameter
t
5
t
6
t
7
t
J
Name
Output-to-Output Skew
Input-to-Output Skew
(Static Phase Error)
[3]
Device-to-Device Skew
[3]
Cycle-to-Cycle Jitter,
Bank A and B Same
Frequency
[3]
[3]
Test Conditions
All Outputs Equally Loaded
Measured at V
DD
/2, REF to FBK
Measured at V
DD
/2
Loaded Outputs
Min.
Typ.
Max.
200
250
500
200
35
Unit
ps
ps
ps
ps
ps
RMS
ps
ps
RMS
ms
Cycle-to-Cycle Jitter,
[3]
Bank A and B Different
Frequency
t
LOCK
PLL Lock Time
[3]
Loaded Outputs
400
70
Stable Power Supply, Valid Clock at REF
1.0
Table 6. Operating Conditions for CY2308AZI–XX Industrial Temperature Devices
Parameter
V
DD
T
A
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Input Capacitance
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
Description
Min.
3.135
–40
Max.
3.465
85
7
500
Unit
V
°C
pF
ms
Table 7. Electrical Characteristics for CY2308AZI-XX Industrial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
I
OL
I
OH
I
DDS
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Current
(–1H)
Output HIGH
(–1H)
Power-down Supply Current
Supply Current
REF = 0V, S1 = V
DD
, S2 = V
DD
Unloaded outputs @ 133 MHz
Loaded outputs @ 133 MHz, C
L
= 10 pF
Table 8. Switching Characteristics for CY2308AZI–XX Industrial Temperature Devices
[4]
Parameter
Name
Reference Frequency
Reference Edge Rate
Reference Duty Cycle
t
1
t
3
t
4
Output Frequency
Duty Cycle
[3]
= t
2
÷
t
1
Rising Edge Rate
[3]
(–1, –2)
Rising Edge Rate
[3]
(–1H)
Falling Edge Rate
[3]
(–1, –2)
Falling Edge
Rate
[3]
(–1H)
C
L
= 10 pF
Measured at V
DD
/2
20% to 80% of V
DD
, C
L
= 15 pF
20% to 80% of V
DD
, C
L
= 15 pF
80% to 20% of V
DD
, C
L
= 15 pF
80% to 20% of V
DD
, C
L
= 15 pF
30% to 70% of V
DD
Test Conditions
Min.
50
0.5
25
50
40.0
0.5
0.8
0.5
0.8
50.0
Typ.
Max.
133
4
75
133
60.0
3
4
3
4
Unit
MHz
V/ns
%
MHz
%
V/ns
V/ns
V/ns
V/ns
Current
[3]
(–1,
–2)
V
OH
= V
DD
– 0.5V
[3]
Test Conditions
CMOS Levels, 30% of V
DD
CMOS Levels, 70% of V
DD
V
IN
= 0V
V
IN
= V
DD
Min.
0.7
Max.
0.25
50.0
10.0
Unit
V
DD
V
DD
µA
µA
mA
(–1, –2)
V
OL
= 0.5V
10
15
–10
–15
50
80.0
110.0
mA
µA
mA
Document #: 38-07377 Rev. *C
Page 4 of 8
CY2308A
Table 8. Switching Characteristics for CY2308AZI–XX Industrial Temperature Devices
[4]
(continued)
Parameter
t
TB
Name
Test Conditions
Min.
Typ.
Max.
650
Unit
ps
Total Timing Budget window, Outputs @ 133 MHz, Tracking Skew Not
Bank A and B Same
Included
Frequency
[5]
Total Timing Budget window,
Bank A and B Different
Frequency
[5]
t
5
t
6
t
7
t
J
Output-to-Output Skew
[3]
Input-to-Output Skew (Static
Phase Error)
[3]
Device-to-Device Skew
[3]
All Outputs Equally Loaded
Measured at V
DD
/2, REF to FBK
Measured at V
DD
/2
850
200
250
500
200
35
400
70
1.0
ps
ps
ps
ps
ps
RMS
ps
ps
RMS
ms
Cycle-to-Cycle Jitter
[3]
, Bank Loaded Outputs
A and B Same Frequency
Cycle-to-Cycle Jitter
[3]
, Bank Loaded Outputs
A and B Different Frequency
t
LOCK
PLL Lock
Time
[3]
Stable Power Supply, Valid Clock at REF
REF. Input to CLKA/CLKB Delay vs. Difference in Loading
Between FBK Pin and CLKA/CLKB Pins
Zero Delay and Skew Control
To close the feedback loop of the CY2308A, the FBK can be
driven from any of the eight available output pins. The output
driving the FBK will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the input-
output delay. See
REF Input to CLK Delay vs. Loading
Difference.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2308A, refer to the appli-
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