®
ISL3856
Data Sheet
April 2002
FN4932.2
P RE LIM IN AR Y
Wireless LAN Access Point Controller
The Intersil ISL3856 Wireless LAN
Access Point Controller is part of
Intersil’s Wireless LAN chip sets
targeting Access Point applications.
The ISL3856 Access Point Controller is an ARM940 core
controller with an onboard MAC to Ethernet (10/100 Base T)
interface. The ISL3856 directly interfaces with the Intersil
HFA386x family of Baseband Processors, offering a
complete end-to-end IEEE 802.11b compliant chip set
solution for wireless LAN products. Protocol and PHY
support are implemented in firmware to allow custom
protocol and different PHY transceivers.
The ISL3856 is a Harvard architecture cached processor.
The separate instruction and data caches in this design are
4kbytes each in size with a four-word line length. A
protection unit allows the memory to be segmented and
protected in a simple manner. There is no virtual physical
address mapping. Write-back cache schemes and write
buffers are used to optimize performance and minimize bus
traffic thus reducing system power consumption. This
Processor Core is implemented using a five-stage pipeline
consisting of fetch, decode, execute, memory and write
stages.
Firmware implements the full IEEE 802.11b Wireless LAN
MAC protocol. It supports Infrastructure mode BSS
operation under DCF, and operation under the optional Point
Coordination Function (PCF). All low-level 802.11 functions
are handled by firmware. Additional firmware functions
specific to access point applications are also available.
The ISL3856 is the industry’s first Access Point on a chip,
which implements both the IEEE 802.11 MAC protocol and
the MAC bridging function, which in alternative solutions
requires a separate external processor. For network
management, an SNMP agent is implemented for access to
the MIB.
Designing wireless protocol systems using the ISL3856 is
made easier with Intersil supplied firmware, software device
drivers, and complete documentation.
Features
• ARM940T Core
• Baseband Processor Interface Providing a Direct Transmit
and Receive Serial Interface to an External Baseband
Processor
• Serial Control Port (SCP), Supporting Serial
Communication for Control of External Devices
• Memory Interfaces Supporting SRAM, ROM and SDRAM
Memories, at 8, 16 or 32 bits
• Real Time Clock
• MII Interface
• 3 General Purpose Timers
• Interrupt Controller
• 16 General Purpose I/Os (GPIO)
• A UART to Enable System Debugging, Multiplexed onto
GPIO Lines
• On-Chip PLL for Clock Generation
• Test Interface Controller (TIC) to Support Manufacturing
Tests
• JTAG Interface for Boundary Scan and Debug Port
• Power Management Capabilities
• IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps
• Part of the Intersil PRISM Wireless LAN Chip Set
• Full Implementation of the MAC Protocol Specified in
IEEE Standards 802.11-1999 and 802.11b
• Operation at 3.3V Supply
• 169 Pin BGA Package Targeted for Compact Gateways
Applications
• High Data Rate Wireless LAN up to 54Mbits
• Residential Gateways
• Wireless LAN Modules such as Wireless Gateways
• Wireless LAN Access Points
• Wireless Bridge Products
• Wireless Point-to-Multipoint Systems
Ordering Information
PART
NUMBER
ISL3856CK
ISL3856CK-T
TEMP. RANGE
(
o
C)
0 to 70
0 to 70
PACKAGE
BGA 11x11
PKG. NO.
V169.11x11
Tape and Reel 1000 Per Reel
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.
ISL3856
ISL3856 Pin Number Assignments
PIN NUMBER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
J1
J2
J3
J4
J5
J6
J7
J8
J9
SIGNAL NAME
SCFRM(O)
MIA(17)
MIA(13)
MIA(10)
MIA(7)
MIA(3)
V
DD
MIA(0)
MIOE-
V
DD
MICLK(3)
MICLK(0)
V
DD
GPIO7
(MAN_RESET)
V
SS
GPIO5
(MDC)
GPIO6
(MDIO)
GPIO2
(Radio_PD)
MIA(8)
V
SS
MIBLS(O)-
V
SS
MICS(O)-
MID(12)
MID(8)
MID(7)
TMS
TCLK
V
DD
BPRXACT
ENRXD(1)
V
DD
V
SS
PMRES
MID(21)
PIN NUMBER
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
F1
F2
F3
F4
SIGNAL NAME
SCFRM(2)
SCCLK
MIA(14)
MIA(11)
V
SS
MIA(2)
MIWE-
MIRDY
MIBLS(2)-
MIAA
MICLK(2)
MICS(2)-
MICS(1)-
GPIO10
(MICLKEN1)
V
DD
PIN NUMBER
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
G1
G2
SIGNAL NAME
GPIO(0)
(PA_PE)
SCTXD
MIA(16)
MIA(15)
MIA(12)
MIA(6)
MIA(4)
MIA(1)
MIBLS(1)-
MISA
MICS(3)-
MID(14)
V
SS
PIN NUMBER
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
M1
M2
M3
M4
M5
M6
M7
M8
M9
SIGNAL NAME
GPIO(4)
(TX_PE)
GPIO(1)
(MD_RDY)
SCRXD
SCFRM(1)
V
DD
MIA(9)
MIA(5)
V
SS
MIBLS(3)-
MICLK(1)
MID15
MID(11)
MID(10)
GPIO14
(CCA)
GPIO12
(PE2)
nTRST
TDI
TDO
BPTXACT
V
SS
NC
MID(25)
MID(30)
MID(1)
MID(31)
MID(0)
BPRXD
BPRXCLK
ENRXD0
ENTXD(0)
ENTXD(3)
NC
NC
ENRXDV
ENCOL
GPIO9
(T/R_SW_BAR)
IN
F5
F6
F7
F8
F9
F10
F11
F12
F13
K1
K2
K3
K4
K5
K6
K7
K8
K9
R
GPIO11
(PE1)
GPIO3
(LED_ETHER)
V
DD
V
SS
MID(13)
MID(9)
V
DD
MID(6)
MID(2)
V
SS
TST(0)
TST(1)
BPTXRDY
ENCRSDV
ENTXER
V
SS
V
SSA
NC
NC
V
E
G3
W
IE
GPIO13
(CAL_EN)
GPIO8(TR_SW)
V
SS
GPIO15
(RESOUT)
V
SS
V
SS
V
SS
V
SS
V
SS
MID(5)
MID(4)
V
DD
MID(3)
BPTXD
BPTXCLK
BPRXRDY
ENTXEN
ENTXD(2)
ENTXCLK
PMXOUT
ENRXD(2)
NC
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
L1
L2
L3
L4
L5
L6
L7
L8
L9
2
ISL3856
ISL3856 Pin Number Assignments
PIN NUMBER
J10
J11
J12
J13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
SIGNAL NAME
MID(28)
MID(26)
MID(27)
MID(29)
V
SS
ENREFCLK
ENRXER
ENTXD(1)
NC
NC
V
DDA
PMXIN
ENRXD(3)
V
DD
NC
V
SS
MID(17)
PIN NUMBER
K10
K11
K12
K13
(Continued)
SIGNAL NAME
MID(20)
MID(23)
MID(24)
V
SS
PIN NUMBER
L10
L11
L12
L13
SIGNAL NAME
NC
MID(18)
V
DD
MID(22)
PIN NUMBER
M10
M11
M12
M13
SIGNAL NAME
NC
NC
MID(16)
MID(19)
Simplified Block Diagram
FREQUENCY
SYNTHESIZER
IN
STATUS/CONTROL
SIGNALS
R
DSSS
BBP
V
E
GPIO
SERIAL
CONTROL
PORT
BASEBAND
PROCESSOR
I/F
W
IE
FLASH
ARM940T
MEMORY
I/F
UP/DOWN
CONVERTER
QUAD IF
MODULATOR
ISL3856
SDRAM
ETHERNET MAC
10/100 MPS
TRANSCEIVER
ETHERNET
3
ISL3856
TABLE 1. MEMORY INTERFACE PINS
PIN NAME
MIA(17)
MIA(16)
MIA(15)
MIA(14)
MIA(13)
MIA(12)
MIA(11)
MIA(10)
MIA(9)
MIA(8)
MIA(7)
MIA(6)
MIA(5)
MIA(4)
MIA(3)
MIA(2)
MIA(1)
MIA(0)
MID(31)
MID(30)
MID(29)
MID(28)
MID(27)
MID(26)
MID(25)
MID(24)
MID(23)
MID(22)
MID(21)
MID(20)
MID(19)
MID(18)
MID(17)
MID(16)
MID(15)
MID(14)
MID(13)
MID(12)
MID(11)
MID(10)
MID(9)
MID(8)
MID(7)
MID(6)
MID(5)
MID(4)
BGA PIN
NUMBER
A2
C3
C4
B3
A3
C5
B4
A4
D6
E6
A5
C6
D7
C7
A6
B6
C8
A8
H12
H10
J13
J10
J12
J11
H9
K12
K11
L13
J9
K10
M13
L11
N13
M12
D11
C12
F8
E11
D12
D13
F9
E12
E13
F11
G10
G11
PIN I/O TYPE
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Output
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
DESCRIPTION
Memory Address Bit 17
Memory Address Bit 16
Memory Address Bit 15
Memory Address Bit 14
Memory Address Bit 13
Memory Address Bit 12
Memory Address Bit 11
Memory Address Bit 10
Memory Address Bit 9
Memory Address Bit 8
Memory Address Bit 7
Memory Address Bit 6
Memory Address Bit 5
Memory Address Bit 4
Memory Address Bit 3
Memory Address Bit 2
Memory Address Bit 1
Memory Address Bit 0
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
IN
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
R
V
E
Memory Bidirectional Data Bus, Bit 31
Memory Bidirectional Data Bus, Bit 30
Memory Bidirectional Data Bus, Bit 29
Memory Bidirectional Data Bus, Bit 28
Memory Bidirectional Data Bus, Bit 27
Memory Bidirectional Data Bus, Bit 26
W
IE
Memory Bidirectional Data Bus, Bit 25
Memory Bidirectional Data Bus, Bit 24
Memory Bidirectional Data Bus, Bit 23
Memory Bidirectional Data Bus, Bit 22
Memory Bidirectional Data Bus, Bit 21
Memory Bidirectional Data Bus, Bit 20
Memory Bidirectional Data Bus, Bit 19
Memory Bidirectional Data Bus, Bit 18
Memory Bidirectional Data Bus, Bit 17
Memory Bidirectional Data Bus, Bit 16
Memory Bidirectional Data Bus, Bit 15
Memory Bidirectional Data Bus, Bit 14
Memory Bidirectional Data Bus, Bit 13
Memory Bidirectional Data Bus, Bit 12
Memory Bidirectional Data Bus, Bit 11
Memory Bidirectional Data Bus, Bit 10
Memory Bidirectional Data Bus, Bit 9
Memory Bidirectional Data Bus, Bit 8
Memory Bidirectional Data Bus, Bit 7
Memory Bidirectional Data Bus, Bit 6
Memory Bidirectional Data Bus, Bit 5
Memory Bidirectional Data Bus, Bit 4
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
4
ISL3856
TABLE 1. MEMORY INTERFACE PINS (Continued)
PIN NAME
MID(3)
MID(2)
MID(1)
MID(0)
MICS(3)-
MICS(2)-
MICS(1)-
MICS(0)-
MICLK(3)
MICLK(2)
MICLK(1)
MICLK(0)
MISA
MIAA
MIBLS(3)-
MIBLS(2)-
MIBLS(1)-
MIBLS(0)-
MIOE-
MIWE-
MIRDY
NOTES:
BGA PIN
NUMBER
G13
F12
H11
H13
C11
B12
B13
E10
A11
B11
D10
A12
C10
B10
D9
B9
C9
E8
A9
B7
B8
PIN I/O TYPE
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS, Bidirectional Data Bus
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Input
DESCRIPTION
Memory Bidirectional Data Bus, Bit 3
Memory Bidirectional Data Bus, Bit 2
Memory Bidirectional Data Bus, Bit 1
Memory Bidirectional Data Bus, Bit 0
Memory Chip Select (one per bank). Bit 3
Memory Chip Select (one per bank). Bit 2
Memory Chip Select (one per bank). Bit 1, MICS(1) is typically
connected to SADRAM.
Memory Chip Select (one per bank). Bit 0, MICS(0) is typically
connected to FLASH memory
Memory Clock Outputs (one per bank) Bit 3
Memory Clock Outputs (one per bank) Bit 2
Memory Clock Outputs (one per bank) Bit 1
Memory Clock Outputs (one per bank) Bit 0
Memory Setup Active Output
Memory Access Active Output
Memory Byte Lane Strobes (one per byte lane), Bit 3
Memory Byte Lane Strobes (one per byte lane), Bit 2
Memory Byte Lane Strobes (one per byte lane), Bit 1
1. MID[15-8] acts as upper address lines for Flash memory.
2. Signals indicated in table which end with a “-” are active low signals.
TABLE 2. GENERAL PURPOSE I/O PIN ASSIGNMENTS DEFINED FOR PRISM II CONNECTIONS
PIN NAME
GPIO(0)
GPIO(1)
GPIO(2)
GPIO(3)
GPIO(4)
GPIO(5)
GPIO(6)
GPIO(7)
GPIO(8)
GPIO(9)
GPIO(10)
GPIO(11)
GPIO(12)
GPIO(13)
GPIO(14)
GPIO(15)
BGA PIN
NUMBER
C1
D2
E5
F5
D1
E3
E4
E1
G2
F3
F1
F4
H2
G1
H1
G4
PIN I/O TYPE
DESCRIPTION OF FUNCTION
(IF OTHER THAN I/O PORT)
PA_PE (Power Amplifier Power Enable Output)
MD_RDY (Input)
RADIO_PD (Radio Power Down Output)
LED_ETHER (Ethernet Activity LED Output)
TX_PE (Transmit Power Enable Output)
MDC (Ethernet Control Interface CLK Output)
MDIO (Ethernet Control Interface I/O)
MAN_RESET (Manual Reset Switch Input)
T/R_SW (Transmit/Receive Switch Output)
T/R_SW# (Transmit/Receive Switch Inverted Output))
MICLKEN1 (Bank 1 Memory Clock Enable Output)
PE1 (Power Enable 1 Output)
PE2 (Power Enable 2 Output)
CAL_EN (Calibration Enable Output)
CCA (Clear Channel Assessment Input)
RESOUT# (Baseband Reset Output), GPIO(15) should be pulled up for regular
chip startup operation
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R
V
E
Memory Byte Lane Strobes (one per byte lane), Bit 0
Memory Output Enable
Memory Write Enable
W
IE
Memory Ready Input
5
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