SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRF137/D
The RF MOSFET Line
RF Power Field-Effect Transistor
N–Channel Enhancement–Mode
. . . designed for wideband large–signal output and driver stages up to
400 MHz range.
•
Guaranteed 28 Volt, 150 MHz Performance
Output Power = 30 Watts
Minimum Gain = 13 dB
Efficiency — 60% (Typical)
•
Small–Signal and Large–Signal Characterization
•
Typical Performance at 400 MHz, 28 Vdc, 30 W
Output = 7.7 dB Gain
•
100% Tested For Load Mismatch At All Phase Angles
With 30:1 VSWR
•
Low Noise Figure — 1.5 dB (Typ) at 1.0 A, 150 MHz
•
Excellent Thermal Stability, Ideally Suited For Class A
Operation
•
Facilitates Manual Gain Control, ALC and Modulation
Techniques
D
MRF137
30 W, to 400 MHz
N–CHANNEL MOS
BROADBAND RF POWER
FET
G
CASE 211–07, STYLE 2
S
Rating
Drain–Source Voltage
Drain–Gate Voltage
(R
GS
= 1.0 MΩ)
Gate–Source Voltage
Drain Current — Continuous
Total Device Dissipation @ T
C
= 25°C
Derate above 25°C
Storage Temperature Range
Operating Junction Temperature
Symbol
V
DSS
V
DGR
V
GS
I
D
P
D
T
stg
T
J
Value
65
65
±40
5.0
100
0.571
–65 to +150
200
Unit
Vdc
Vdc
Vdc
Adc
Watts
W/°C
°C
°C
MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
Symbol
R
θJC
Max
1.75
Unit
°C/W
Handling and Packaging
— MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 6
1
MRF137
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (V
GS
= 0, I
D
= 10 mA)
Zero Gate Voltage Drain Current (V
DS
= 28 V, V
GS
= 0)
Gate–Source Leakage Current (V
GS
= 20 V, V
DS
= 0)
V
(BR)DSS
I
DSS
I
GSS
65
—
—
—
—
—
—
4.0
1.0
Vdc
mAdc
µAdc
ON CHARACTERISTICS
Gate Threshold Voltage (V
DS
= 10 V, I
D
= 25 mA)
Forward Transconductance (V
DS
= 10 V, I
D
= 500 mA)
V
GS(th)
g
fs
1.0
500
3.0
750
6.0
—
Vdc
mmhos
DYNAMIC CHARACTERISTICS
Input Capacitance (V
DS
= 28 V, V
GS
= 0, f = 1.0 MHz)
Output Capacitance (V
DS
= 28 V, V
GS
= 0, f = 1.0 MHz)
Reverse Transfer Capacitance (V
DS
= 28 V, V
GS
= 0, f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
48
54
11
—
—
—
pF
pF
pF
FUNCTIONAL CHARACTERISTICS
Noise Figure
(V
DS
= 28 Vdc, I
D
= 1.0 A, f = 150 MHz)
Common Source Power Gain
(V
DD
= 28 Vdc, P
out
= 30 W,
I
DQ
= 25 mA)
f = 150 MHz (Figure 1)
f = 400 MHz (Figure 14)
η
ψ
No Degradation in Output Power
NF
G
ps
13
—
50
16
7.7
60
—
—
—
%
—
1.5
—
dB
dB
Drain Efficiency (Figure 1)
(V
DD
= 28 Vdc, P
out
= 30 W, f = 150 MHz, I
DQ
= 25 mA)
Electrical Ruggedness (Figure 1)
(V
DD
= 28 Vdc, P
out
= 30 W, f = 150 MHz, I
DQ
= 25 mA,
VSWR 30:1 at All Phase Angles)
R4
BIAS
ADJUST
+
-
RFC2
C9
C10
+
V
DD
= 28 V
R3
D1
C7
C8
RFC1
R2
C6
RF
INPUT
C1
L1
R1
C5
L2
DUT
L3
RF
OUTPUT
C2
C3
C4
C1 — Arco 403, 3.0–35 pF, or equivalent
C2 — Arco 406, 15–115 pF, or equivalent
C3 — 56 pF Mini–Unelco, or equivalent
C4 — Arco 404, 8.0–60 pF, or equivalent
C5 — 680 pF, 100 Mils Chip
C6 — 0.01
µF,
100 V, Disc Ceramic
C7 — 100
µF,
40 V
C8 — 0.1
µF,
50 V, Disc Ceramic
C9, C10 — 680 pF Feedthru
D1 — 1N5925A Motorola Zener
L1 — 2 Turns, 0.29″ ID, #18 AWG Enamel, Closewound
L2 — 1–1/4 Turns, 0.2″ ID, #18 AWG Enamel, Closewound
L3 — 2 Turns, 0.2″ ID, #18 AWG Enamel, Closewound
RFC1 — 20 Turns, 0.30″ ID, #20 AWG Enamel, Closewound
RFC2 — Ferroxcube VK–200 — 19/4B
R1 — 10 kΩ, 1/2 W Thin Film
R2 — 10 kΩ, 1/4 W
R3 — 10 Turns, 10 kΩ
R4 — 1.8 kΩ, 1/2 W
Board — G10, 62 Mils
Figure 1. 150 MHz Test Circuit
REV 6
2
50
Pout , OUTPUT POWER (WATTS)
40
30
20
10
0
f = 100 MHz
Pout , OUTPUT POWER (WATTS)
150 MHz
200 MHz
20
f = 100 MHz
15
150 MHz
200 MHz
10
V
DD
= 28 V
I
DQ
= 25 mA
5
V
DD
= 13.5 V
I
DQ
= 25 mA
0
0.5
1
1.5
P
in
, INPUT POWER (WATTS)
2
0
0
1
2
P
in
, INPUT POWER (WATTS)
3
4
Figure 2. Output Power versus Input Power
Figure 3. Output Power versus Input Power
40
Pout , OUTPUT POWER (WATTS)
Pout , OUTPUT POWER (WATTS)
f = 400 MHz
I
DQ
= 25 mA
30
V
DD
= 28 V
50
40
30
20
10
0
P
in
= 1 W
0.5 W
0.25 W
20
V
DD
= 13.5 V
10
0
I
DQ
= 25 mA
f = 100 MHz
12
20
24
16
V
DD
, SUPPLY VOLTAGE (VOLTS)
28
0
2
4
6
P
in
, INPUT POWER (WATTS)
8
10
Figure 4. Output Power versus Input Power
Figure 5. Output Power versus Supply Voltage
50
Pout , OUTPUT POWER (WATTS)
Pout , OUTPUT POWER (WATTS)
40
30
20
10
0
12
P
in
= 1.5 W
50
40
30
20
10
0
12
P
in
= 2 W
1.5 W
0.75 W
0.75 W
0.5 W
I
DQ
= 25 mA
f = 150 MHz
16
20
24
V
DD
, SUPPLY VOLTAGE (VOLTS)
28
I
DQ
= 25 mA
f = 200 MHz
16
20
24
V
DD
, SUPPLY VOLTAGE (VOLTS)
28
Figure 6. Output Power versus Supply Voltage
Figure 7. Output Power versus Supply Voltage
REV 6
3
50
Pout , OUTPUT POWER (WATTS)
40
30
20
2W
10
0
12
I
DQ
= 25 mA
f = 400 MHz
20
24
16
V
DD
, SUPPLY VOLTAGE (VOLTS)
28
Pout , OUTPUT POWER (WATTS)
30
25
20
15
10
5
0
-9
-8
-6
-4
-2
0
V
GS
, GATE-SOURCE VOLTAGE (VOLTS)
1
2
3
TYPICAL DEVICE SHOWN,
V
GS(th)
= 3 V
V
DD
= 28 V
I
DQ
= 25 mA
P
in
= CONSTANT
P
in
= 8 W
5W
400 MHz
150 MHz
Figure 8. Output Power versus Supply Voltage
Figure 9. Output Power versus Gate Voltage
VGS, GATE SOURCE VOLTAGE (NORMALIZED)
3
I D, DRAIN CURRENT (AMPS)
TYPICAL DEVICE SHOWN,
V
GS(th)
= 3 V
2
1.02
1
0.98
0.96
0.94
0.92
-25
V
DS
= 28 V
I
D
= 1.25 A
1A
750 mA
1
V
DS
= 10 V
500 mA
25 mA
200 mA
0
1
2
3
4
5
6
V
GS
, GATE-SOURCE VOLTAGE (VOLTS)
7
0
25
50
75
100
125
T
C
, CASE TEMPERATURE (°C)
150
175
Figure 10. Drain Current versus Gate Voltage
(Transfer Characteristics)
Figure 11. Gate Source Voltage versus
Case Temperature
200
180
140
120
100
80
60
40
20
0
0
4
8
12
16
20
V
DS
, DRAIN-SOURCE VOLTAGE (VOLTS)
24
28
C
iss
C
rss
C
oss
I D, DRAIN CURRENT (AMPS)
160
C, CAPACITANCE (pF)
V
GS
= 0 V
f = 1 MHz
10
5
2
1
0.5
T
C
= 25°C
0.1
1
2
5
10
20
V
DS
, DRAIN-SOURCE VOLTAGE (VOLTS)
60
100
Figure 12. Capacitance versus
Drain–Source Voltage
Figure 13. DC Safe Operating Area
REV 6
4
R4
BIAS
ADJUST
R3
D1
C9
R2
R1
RF
INPUT
Z1
C5
C1
C6
C2
Z2
Z3
DUT
RFC1
C10
+
-
C11
RFC2
V
DD
= 28 V
C12
C13
C8
Z4
Z5
Z6
RF
OUTPUT
C7
C3
C4
C1, C2, C3, C4 — 0–20 pF Johanson, or equivalent
C5, C8 — 270 pF, 100 Mil Chip
C6, C7 — 24 pF Mini–Unelco, or equivalent
C9 — 0.01
µF,
100 V, Disc Ceramic
C10 — 100
µF,
40 V
C11 — 0.1
µF,
50 V, Disc Ceramic
C12, C13 — 680 pF Feedthru
D1 — 1N5925A Motorola Zener
R1, R2 — 10 kΩ, 1/4 W
R3 — 10 Turns, 10 kΩ
R4 — 1.8 kΩ, 1/2 W
Z1 — 2.9″ x 0.166″ Microstrip
Z2, Z4 — 0.35″ x 0.166″ Microstrip
Z3 — 0.40″ x 0.166″ Microstrip
Z5 — 1.05″ x 0.166″ Microstrip
Z6 — 1.9″ x 0.166″ Microstrip
RFC1 — 6 Turns, 0.300″ ID, #20 AWG Enamel, Closewound
RFC2 — Ferroxcube VK–200 — 19/4B
Board — Glass Teflon, 62 Mils
Figure 14. 400 MHz Test Circuit
Z
in
150
200
200
400
150
f = 100 MHz
Z
OL
*
400
f = 100 MHz
V
DD
= 28 V, I
DQ
= 25 mA,
P
out
= 30 W
f
MHz
100
150
200
400
Z
in
{
Ohms
2.11 - j11.07
1.77 - j7.64
1.85 - j3.75
1.74 + j3.62
Z
OL
*
Ohms
8.02 - j2.89
5.75 - j3.02
3.52 - j2.67
2.88 - j1.52
Z
OL
* = Conjugate of the optimum load impedance
into which the device output operates at a given out
put power, voltage and frequency.
Figure 15. Large–Signal Series Equivalent Input and Output Impedance, Z
in
, Z
OL
*
REV 6
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
