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HY5DU663222Q-5: 产品描述DDR DRAM, 2MX32, 1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100; 产品类别存储存储; 文件大小267KB，共27页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5DU663222Q-5概述

DDR DRAM, 2MX32, 1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100

HY5DU663222Q-5规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	QFP
包装说明	LQFP, QFP100,.63X.87
针数	100
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	1 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	200 MHz
I/O 类型	COMMON
交错的突发长度	2,4,8
JESD-30 代码	R-PQFP-G100
长度	20 mm
内存密度	67108864 bit
内存集成电路类型	DDR DRAM
内存宽度	32
功能数量	1
端口数量	1
端子数量	100
字数	2097152 words
字数代码	2000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	2MX32
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LQFP
封装等效代码	QFP100,.63X.87
封装形状	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	2.8 V
认证状态	Not Qualified
座面最大高度	1.6 mm
自我刷新	YES
连续突发长度	2,4,8
最大待机电流	0.01 A
最大压摆率	0.47 mA
最大供电电压 (Vsup)	2.94 V
最小供电电压 (Vsup)	2.66 V
标称供电电压 (Vsup)	2.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.65 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	14 mm
Base Number Matches	1

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HY5DU663222Q

64M(2Mx32) DDR SDRAM

HY5DU663222Q

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.9/ Dec. 01

HY5DU663222Q

PIN DESCRIPTION

CK, /CK

TYPE

Input

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data.

Data input / output pin : Data Bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CKE

Input

/CS

Input

BA0, BA1

Input

A0 ~ A10

Input

/RAS, /CAS, /WE

Input

DM0 ~ DM3

Input

DQS

DQ0 ~ DQ31

DDQ

SSQ

REF

I/O

Supply

Rev. 0.9 / Dec. 01

HY5DU663222Q-5相似产品对比

	HY5DU663222Q-5	HY5DU663222Q-6	HY5DU663222Q-55	HY5DU663222Q-7
描述	DDR DRAM, 2MX32, 1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100	DDR DRAM, 2MX32, 1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100	DDR DRAM, 2MX32, 1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100	DDR DRAM, 2MX32, 1.1ns, CMOS, PQFP100, 20 X 14 MM, 0.65 MM PITCH, LQFP-100
是否无铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合
零件包装代码	QFP	QFP	QFP	QFP
包装说明	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87
针数	100	100	100	100
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	1 ns	1 ns	1 ns	1.1 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	200 MHz	166 MHz	183 MHz	143 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON
交错的突发长度	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 代码	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
长度	20 mm	20 mm	20 mm	20 mm
内存密度	67108864 bit	67108864 bit	67108864 bit	67108864 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	32	32	32	32
功能数量	1	1	1	1
端口数量	1	1	1	1
端子数量	100	100	100	100
字数	2097152 words	2097152 words	2097152 words	2097152 words
字数代码	2000000	2000000	2000000	2000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C
组织	2MX32	2MX32	2MX32	2MX32
输出特性	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LQFP	LQFP	LQFP	LQFP
封装等效代码	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	2.8 V	2.8 V	2.8 V	2.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm
自我刷新	YES	YES	YES	YES
连续突发长度	2,4,8	2,4,8	2,4,8	2,4,8
最大待机电流	0.01 A	0.01 A	0.01 A	0.01 A
最大压摆率	0.47 mA	0.41 mA	0.44 mA	0.37 mA
最大供电电压 (Vsup)	2.94 V	2.94 V	2.94 V	2.94 V
最小供电电压 (Vsup)	2.66 V	2.66 V	2.66 V	2.66 V
标称供电电压 (Vsup)	2.8 V	2.8 V	2.8 V	2.8 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	14 mm	14 mm	14 mm	14 mm
厂商名称	SK Hynix(海力士)	-	SK Hynix(海力士)	SK Hynix(海力士)

HY5DU663222Q-5

HY5DU663222Q-5概述

HY5DU663222Q-5规格参数

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