RM7900
Microprocessor
Released
RM7900 64-bit MIPS RISC Microprocessor with Integrated L2 Cache and EJTAG
FEATURES
• New high performance MIPS64-
compatible Instruction Set Architecture
with integrated L2 cache and EJTAG.
•
668, 750, 835, and 900 MHz
operating frequency.
•
1890 Dhrystone 2.1 MIPS @
900 MHz.
•
Dual-issue superscalar 7-stage
pipeline.
•
16 Kbyte, 4-way set associative L1
Instruction cache.
•
16 Kbyte, 4-way set associative L1
Data cache.
•
256 Kbyte, 4-way set associative L2
cache with industry best 5-cycle
access latency.
•
Fast Packet Cache to assists
processing of packet data.
•
8K entry branch prediction table.
Fully associative 64-entry TLB with
dual pages.
•
High-performance Floating Point
Unit (IEEE 754).
•
Fixed-point DSP instructions such
as Multiply/Add, Multiply/Subtract,
and 3 Operand Multiply.
• High-performance system interface:
•
64-bit multiplexed address/data bus
(SysAD) bus.
•
Multiple outstanding reads with out-
of-order return.
•
1600 Mbyte/s peak throughput.
•
200 MHz maximum frequency using
HSTL signaling on the SysAD bus.
•
SysAD bus supports 1.5 V, 2.5 V,
3.3 V I/O logic.
•
Processor clock multipliers 2, 3, 3.5,
4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9,
10, 11, 12, 13, 14, 15, 16, 17.
•
• Integrated external cache controller
(up to 8 Mbytes).
• Integrated on-chip EJTAG capability.
• A 64-entry dynamic Trace Buffer for
use in real-time trace and debug.
• Two 32-bit virtually-addressed Watch
registers.
• Integrated performance counters:
•
2 independent 32-bit counters.
•
Counts over 30 processor events
including miss predicted branches.
•
Enables full characterization and
analysis of application software.
BLOCK DIAGRAM
On-Chip Debug
64-bit Integer Unit
Dual-Issue Superscalar
Integer Multiplier
Branch Trace Buffer
64-bit Floating Point Unit
Double/Single IEEE-754
Instruction Dispatch
8K Entry Branch History Tbl
Instruction Cache
16 KB, 4-way
Line Lockable
Memory Manager
64-Entry, Dual Page
Data Cache
16 KB, 4-way
Line Lockable
Interface Unit
System Control
Secondary Cache
256 KB, 4-way
Line Lockable
E9000 Core
SysAD
System Interface
Interrupt
Interface
EJTAG/JTAG
Controller
Cache Test
Mode
PLL & Clock
PMC-2030269
Issue 3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2005
All rights reserved.
RM7900 Microprocessor
RM7900 64-bit MIPS RISC Microprocessor with Integrated L2 Cache and EJTAG
PACKAGING
• Available in a 304-pin EPBGA
package, 31 x 31 mm.
• Pin compatible with RM7000A,
RM7000B, and RM7000C products.
DEVELOPMENT TOOLS
• Operating Systems:
•
Linux
•
VxWorks
• EJTAG Emulators
•
Wind River
•
Corelis
• Evaluation Boards
•
Momentum Computer
•
Marvell Semiconductor
• Companion Chips
•
Marvell Semiconductor (MV-64340,
GT-64240)
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
Voice Gateways
Multi-Service Access Platforms
DSLAMs/Access Concentrators
Remote Access Switches
Web Switches
Layer 3 Switches
Backbone Switches/Routers
RAIDs
Set Top Boxes
Networked Printers
Cellular Base Stations
TYPICAL APPLICATIONS
RM7900
64-Bit
200 MHz
L3 Cache
Marvell
MV-64340
or
ASIC
64-Bit
183 MHz
DDR SDRAM
PCI-(X) Bus
2x32/64-bit @ 66 MHz
2x64-bit
Data Buffer
64-bit
32-bit
32-bit
8-bit
Boot-Flash
PCI-to-PCI
Bridge
GbE MAC
GbE MAC
Flash Disk
Watchdog, I
2
C
& Control
Registers
Dual UART
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-2030269 (R3)
© Copyright PMC-Sierra, Inc. 2005. All
rights reserved.
For a complete list of PMC-Sierra’s
trademarks and registered trademarks,
visit: http://www.pmc-sierra.com/legal/.
Other product and company names
mentioned herein may be the trademarks of
their respective owners.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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