IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
CMOS 18-BIT TTL/GTLP
UNIVERSAL BUS
TRANSCEIVER
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bidirectional interface between GTLP and TTL logic levels
Edge Rate Control Circuit reduces output noise
V
REF
pin provides reference voltage for receiver threshold
CMOS technology for low power dissipation
Special PVT Compensation circuitry to provide consistent perfor-
mance over variations of process, supply voltage, and temperature
5V tolerant inputs and outputs on A-Port
Bus-Hold to eliminate the need for external pull-up resistors for
unused inputs to A-Port
Power up/down high-impedance
TTL-compatible Driver and Control inputs
High Output source/sink ±32mA on A-Port pins
Flow-through architecture optimizes system layout
D-type latch and flip-flop architecture for data flow in clocked,
transparent, or latched mode
Open drain on GTLP to support wired OR connection
Available in SSOP and TSSOP packages
IDT74GTLP16612
DESCRIPTION:
The GTLP16612 is an 18-bit universal bus transceiver. It provides
signal level translation, from TTL to GTLP, for applications requiring a high-
speed interface between cards operating at TTL logic levels and back-
planes operating at GTLP logic levels. GTLP provides reduced output
swing (<1V), reduced input threshold levels, and output edge-rate control
to minimize signal setting times. The GTLP16612 is a derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates
internal edge-rate control, which is process, voltage, and temperature
(PVT) compensated.
GTLP output low voltage is less than 0.5V. The output high is 1.5V, and
the receiver threshold is 1V.
FUNCTIONAL BLOCK DIAGRAM
OEAB
1
CEAB
56
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
CEBA
29
OEBA
27
ONE OF 18 CHANNELS
CE
1D
C1
CE
1D
C1
CLK
CLK
A1
3
GTLP
54
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5477/2
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
(3.3V)
A
4
A
5
A
6
GND
Q
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
(3.3V)
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CEAB
CLKAB
B
1
GND
B
2
B
3
V
CCQ
(5V)
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
REF
B
16
B
17
GND
B
18
CLKBA
CEBA
ABSOLUTE MAXIMUM RATINGS
(1,2)
Symbol
V
CC
V
CCQ
V
I
V
O
V
O
I
OL
I
OH
I
OL
I
IK
I
OK
I
OK
T
STG
DC Input Voltage
DC Output Voltage, 3-State
DC Output Voltage, Active
DC Output Sink Current into A-port
DC Output Source Current from A-port
DC Output Sink Current into B-port
(in the LOW state)
DC Input Diode Current V
I
< 0V
DC Output Diode Current V
O
< 0V
DC Output Diode Current V
O
> V
CC
Storage Temperature
–50
–50
+50
–65 to +150
mA
mA
mA
°C
–0.5 to +7
–0.5 to +7
–0.5 to V
CC
+ 0.5
64
–64
80
V
V
V
mA
mA
mA
Rating
Supply Voltage
Max.
–0.5 to +7
Unit
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Unused inputs without Bus-Hold must be held HIGH or LOW.
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Symbol
C
IN
C
I
/
O
C
I
/
O
Parameter
(1)
Control Pins
A-Port
B-Port
Conditions
V
I
= V
CCQ
or 0
V
I
= V
CCQ
or 0
V
I
= V
CCQ
or 0
Typ.
(2)
8
9
6
Max.
—
—
—
Unit
pF
pF
pF
NOTES:
1. As applicable to the device type.
2. All typical values are at V
CC
= 3.3V and V
CCQ
= 5V.
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
CLKAB
CLKBA
V
REF
A
1
- A
18
B
1
- B
18
Description
(1)
A-to-B Output Enable (Active LOW)
B-to-A Output Enable (Active LOW)
A-to-B Clock Enable (Active LOW)
B-to-A Clock Enable (Active LOW)
A-to-B Latch Enable (Transparent HIGH)
B-to-A Latch Enable (Transparent HIGH)
A-to-B Clock Pulse
B-to-A Clock Pulse
GTLP Input Reference Voltage
A-to-B TTL Data Inputs or B-to-A 3-State Outputs
B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs
SSOP/ TSSOP
TOP VIEW
NOTE:
1. A-Port pins have Bus-Hold. All other pins are standard input, output, or I/O.
2
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING
CONDITIONS
(1)
Symbol
V
CC
V
CCQ
V
TT
V
I
I
OH
I
OL
I
OL
T
A
Bus Termination Voltage
Input Voltage on A-Port and Control Pins
HIGH Level Output Current (A-Port)
LOW Level Output Current (A-Port)
LOW Level Output Current (B-Port)
Operating Temperature
Supply Voltage
Rating
Recommended
3.15 to 3.45
4.75 to 5.25
1.35 to 1.65
0 to 5.5
-32
+32
+34
–40 to +85
V
V
mA
mA
mA
°C
Unit
V
FUNCTIONAL DESCRIPTION:
The GTLP16612 combines a universal transceiver function with a TTL
to GTLP translation. The A-Port and control pins operate at LVTTL or 5V
TTL levels while the B-Port operates at GTLP levels. The transceiver logic
includes D-type latches and D-type flip-flops to allow data flow in transparent,
latched, and clock mode.
NOTE:
1. Unused inputs without Bus-Hold must be held HIGH or LOW.
FUNCTION TABLE
(1,2)
Inputs
CEAB
X
L
L
X
X
L
L
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A data flow is similar, but uses
OEBA,
LEBA, CLKBA, and
CEBA.
3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
4. Output level before the indicated steady-state input conditions were established.
Outputs
CLKAB
X
H
L
X
X
↑
↑
X
Ax
X
X
X
L
H
L
H
X
Bx
Z
B
0
B
0
(3)
(4)
Mode
Latched
storage
of A data
Transparent
Clocked storage
of A data
Clock Inhibit
OEAB
H
L
L
L
L
L
L
L
LEAB
X
L
L
H
H
L
L
L
L
H
L
H
B
0
(4)
3
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
REF
= 1V, V
CC
= 3.3V ± 5%, V
CCQ
= 5V ± 5%
Symbol
V
IH
V
IL
V
REF
V
IK
V
OH
A-Port
Parameter
B-Port
All Other ports
B-Port
All Other ports
—
—
—
—
—
—
—
V
CC
= 3.15V I
I
= –18mA
V
CCQ
= 4.75V
V
CC
, V
CCQ
= Min to Max
(2)
V
CC
= 3.15V
V
CCQ
= 4.75V
V
OH
A-Port
V
CC
, V
CCQ
= Min to Max
V
CC
= 3.15V
V
CCQ
= 4.75V
B-Port
I
I
Control Pins
A-Port
V
CC
= 3.15V
V
CCQ
= 4.75V
V
CC
, V
CCQ
= 0 or Max
V
CC
= 3.45V
V
CCQ
= 5.25V
B-Port
I
OFF
I
I
(HOLD)
I
OZH
I
OZL
I
CCQ
(V
CCQ
)
A-Port
A-Port
A-Port
B-Port
A-Port
B-Port
A or B Ports
V
CC
= 3.45V
V
CCQ
= 5.25V
V
CC
= V
CCQ
= 0
V
CC
= 3.15V
V
CCQ
= 4.75V
V
CC
= 3.45V
V
CCQ
= 5.25V
V
CC
= 3.45V
V
CCQ
= 5.25V
V
CC
= 3.45V
V
CCQ
= 5.25V
I
O
= 0
V
I
= V
CCQ
or GND
I
CC
(V
CC
)
A or B Ports
V
CC
= 3.45V
V
CCQ
= 5.25V
I
O
= 0
V
I
= V
CCQ
or GND
∆I
CC
(3)
A-Port and Control Pins
V
CC
= 3.45V
V
CCQ
= 5.25V
A or Control Inputs at
V
CC
or GND
NOTES:
1. All typical values are at V
CC
= 3.3V, V
CCQ
= 5V, and T
A
= 25°C.
2. For conditions shown as Max. or Min., use appropriate value specified under Recommended Operating Conditions.
3.
∆I
CC
is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
(2)
Test Conditions
Min.
V
REF
+ 0.1
2
0
—
—
—
V
CC
–0.2
2.4
2
—
—
—
—
—
—
—
—
—
—
75
–20
—
—
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
0
0
0
0
Max.
V
TT
—
V
REF
– 0.1
0.8
—
–1.2
—
—
—
0.2
0.5
Unit
V
V
V
V
I
OH
= –100µA
I
OH
= –8mA
I
OH
= –32mA
I
OL
= 100µA
I
OL
= 32mA
I
OL
= 34mA
V
I
= 5.5V or 0V
V
I
= 5.5V
V
I
= V
CC
V
I
= 0
V
I
= V
CCQ
V
I
= 0
V
I
or V
O
= 0 to 4.5V
V
I
= 0.8V
V
I
= 2V
V
O
= 3.45 V
V
O
= 1.5V
V
O
= 0
V
O
= 0.65V
Outputs HIGH
Outputs LOW
Outputs Disabled
Outputs HIGH
Outputs LOW
Outputs Disabled
One Input at 2.7V
V
V
0.65
±10
20
1
–30
5
–5
100
—
—
1
5
–20
–10
40
40
40
1
1
1
1
mA
mA
mA
µA
µA
µA
µA
µA
4
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1,2)
IDT74GTLP16612
Symbol
f
CLOCK
t
W
t
W
t
S
t
S
t
S
t
S
t
S
t
S
t
H
t
H
t
H
t
H
t
H
t
H
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
RISE
t
FALL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
NOTES:
1. See Test Circuits and Waveforms. T
A
= –40°C to +85°C.
2. Unless otherwise noted, V
REF
= 1V, C
L
= 30pF for B-Port, and C
L
= 50pF for A-Port.
3. Typical values are at V
CC
= 3.3V, V
CCQ
= 5V, and T
A
= 25°C.
Parameter
Max Clock Frequency
Pulse Duration, LEAB or LEBA HIGH
Pulse Duration, CLKAB or CLKBA HIGH or LOW
Setup Time, Ax before CLKAB
↑
Setup Time, Bx before CLKBA
↑
Setup Time, Ax before LEAB
↓
Setup Time, Bx before LEBA
↓
Setup Time,
CEAB
before CLKAB
↑
Setup Time,
CEBA
beforeCLKBA
↑
Hold Time, Ax after CLKAB
↑
Hold Time, Bx after CLKBA
↑
Hold Time, Ax after LEAB
↓
Hold Time, Bx after LEBA
↓
Hold Time,
CEAB
after CLKAB
↑
Hold Time,
CEBA
afterCLKBA
↑
Ax to Bx
LEAB to Bx
CLKAB to Bx
OEAB
to Bx
Transition Time, B outputs (20% to 80%)
Bx to Ax
LEBA to Ax
CLKBA to Ax
OEBA
to Ax
Min.
175
3
3.2
0.5
3.1
1.3
3.7
0.4
1
1.5
0
0.5
0
1.5
1.7
1
1
1.8
1.5
1.8
1.5
1.6
1.3
—
2
1.4
2.1
1.9
2.3
2.2
1.5
1.9
Typ.
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.3
5
4.5
5.3
4.6
5.4
4.4
6.1
2.6
5.6
5
4.2
3.3
4.4
3.5
5
3.9
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6.5
8.2
6.7
8.6
6.7
8.7
6.2
9.8
—
8.2
7.2
6.3
5
6.8
5.2
6.2
7.9
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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