Quad Line Receiver
Recei
eceiv
Austin Semiconductor, Inc.
AS10515F16MIL
Quad Line Receiver
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Equivalent Screening - 883 1.2.2
PIN ASSIGNMENT
(Top View)
16-Pin FlatPack (F)
GENERAL DESCRIPTION
The AS10515F16MIL is a quad differential amplifier
designed for use in sensing differential signals over long lines.
The base bias supply (V
BB
) is made available at pin 9 to make
the device useful as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the AS10515F16MIL with
excellent common mode noise rejection. If any amplifier in
a package is not used, one input of that amplifier must be
connected to V
BB
(pin 9) to prevent upsetting the current
source bias network.
• P
D
= 150mW Max/Pkg (No Load)
• t
pd
= 2.0ns typ
• t
r
, t
f
= 2.0ns type (20% - 80%)
D
IN\
C
OUT
D
OUT
V
CC2
V
CC1
A
OUT
B
OUT
A
IN\
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D
IN
C
IN
C
IN\
V
BB
V
EE
B
IN\
B
IN
A
IN
BURN-IN CONDITIONS:
V
TT
= -2.0V MAX/ -2.2V MIN
V
EE
= -5.7V MAX/ -5.2V MIN
V
BB
= All pins designated for V
BB
must be tied together, no
external voltage applied.
NOTES
1. V
BB
to be used to supply bias to the AS10515F16MIL only and
bypassed (when used) with 0.01 µF to 0.1 µF capacitor.
2. When the input pin with the bubble goes positive, the output goes
negative.
PIN ASSIGNMENTS
FUNCTION
V
CC1
A
OUT
B
OUT
A
IN
\
A
IN
B
IN
B
IN
\
V
EE
V
BB
C
IN
\
C
IN
D
IN
D
IN
\
C
OUT
D
OUT
V
CC2
FLATS
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
BURN-IN
(CONDITION C)
GND
51
Ω
to V
TT
51
Ω
to V
TT
V
BB
GND
GND
V
BB
V
EE
V
BB
V
BB
GND
GND
V
BB
51
Ω
to V
TT
51
Ω
to V
TT
GND
LOGIC DIAGRAM
4
5
6
7
10
11
12
13
V
BB
2
3
14
15
9
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS10515F16MIL
Rev. 2.1 07/06
1
Quad Line Receiver
Recei
eceiv
Austin Semiconductor, Inc.
Channel A
V
CC
= 2.0V ± 0.005V
AS10515F16MIL
Channel B
Coax B
Coax A
25 µF
± 20%
0.1 µF
± 20%
R
1
*Pulse
Generator
Input
Coax
D.U.T.
C
L
*Pulse Generator must be capable of
rise and fall times of 2.0ns ± 0.2ns.
0.1 µF ±20%
NOTES:
1. t
r
= t
f
= 2.0ns ±0.2ns measured at (20% - 80%)
V
EE
= -3.2V ±0.005V
2. P
W
> 20ns
3. P
RF
= 1.0 MHz
4. R
1
= 50
Ω
resistor in series with 50
Ω
coax constituting the 100
Ω
load.
5. Unused outputs should be loaded 100
Ω
to ground.
6. 2:1 divider may be used.
R
1
= 50
Ω
resistor in series with
a 50
Ω
coax cable constituting
the 100
Ω
load.
t
r
t
f
PS1
V
IN
80%
50%
20%
> 20ns
80%
50%
20%
PS2
t
TLH
80%
50%
20%
80%
50%
20%
t
THL
V
OUT
V
OUT
\
t
PLH
t
PHL
80%
50%
20%
t
PHL
t
PLH
80%
50%
20%
t
THL
AS10515F16MIL
Rev. 2.1 07/06
t
TLH
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Figure 1. Switching Test Circuit and Waveforms
2
AS10515F16MIL
Rev. 2.1 07/06
QUIESCENT LIMIT TABLE*
Test
Temperature
V
IH1
-0.78
-0.63
-0.88
-1.92
-1.255 -1.510 +1.01
+0.28
-3.2
-5.2
-5.2
-1.82
-1.000 -1.400 +1.24
+0.36
-3.2
-5.2
-5.2
-1.85
-1.105 -1.475 +1.11
+0.31
-3.2
-5.2
-5.2
V
IL1
V
IH2
V
IL2
P
S1
P
S2
V
EEL
V
EE
V
CB
T
A
= 25°C
T
A
= 125°C
T
A
= -55°C
Test Voltage Values (Volts)
* ELECTRICAL CHARACTERISTICS
Each MECL 10K series circuit has been designed to meet
the dc specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs
are terminated through a 100
Ω
resistor to -2.0 volts.
SYMBOL PARAMETER
TEST VOLTAGE APPLIED TO PINS BELOW:
Pinouts referenced are for F package, check Pin Assignments
V
CC
= 0V, Output Load = 100
Ω
to -2.0V
Functional
Parameters:
V
IH1
V
IL1
8
8
5, 6, 11, 12 4, 7, 10, 13
4, 7, 10, 13 5, 6, 11, 12
8
8
8
4-7
10 - 13
8
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
4-7
10 - 13
1, 16
V
IH2
V
IL2
V
EE
V
CC
5, 6, 11, 12 4, 7, 10, 13
4, 7, 10, 13 5, 6, 11, 12
-1.08
V
V
V
V
mA
165
-1.5
µA
µA
-0.88
V
UNITS
LIMITS
+25°C
+125°C
-55°C
Subgroup 1 Subgroup 2 Subgroup 3
MIN MAX MIN MAX MIN MAX
P.U.T.
2, 3 ,14, 15
2, 3 ,14, 15
2, 3 ,14, 15
2, 3 ,14, 15
9
8
4-7
10 - 13
4-7
10 - 13
V
OH
-0.93
-0.78 -0.825 -0.63
V
OL
-1.10
-0.88
-1.85
-1.62
-1.82 -1.545 -1.92 -1.655
V
OH1
-0.95
-0.78 -0.845 -0.63
Austin Semiconductor, Inc.
3
-1.44
-29
-1.32
V
OL1
-1.85
-1.60
-1.82 -1.525 -1.92 -1.635
**V
BB
-1.35
-1.23
-1.24
-1.12
I
EE
-26
-29
***
4-7
11 - 13
4-7
11 - 13
4-7
11 - 13
4-7
11 - 13
5, 6
11, 12
5, 6
11, 12
I
IH
High Output
Voltage
Low Output
Voltage
High Output
Voltage
Low Output
Voltage
Reference
Voltage
Power Supply
Current
Input Current
High
95
165
I
CBO
Input Leakage
Current
-1.0
-1.0
Quad Line Receiver
Recei
eceiv
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS10515F16MIL
** Connected to pin 9.
*** Measure voltage on pin 9 while it is connected to other pins.
AS10515F16MIL
Rev. 2.1 07/06
QUIESCENT LIMIT TABLE*
Test
Temperature
V
IH1
-0.78
-0.63
-0.88
-1.92
-1.255 -1.510 +1.01
+0.28
-3.2
-5.2
-5.2
-1.82
-1.000 -1.400 +1.24
+0.36
-3.2
-5.2
-5.2
-1.85
-1.105 -1.475 +1.11
+0.31
-3.2
-5.2
-5.2
V
IL1
V
IH2
V
IL2
P
S1
P
S2
V
EEL
V
EE
V
CB
T
A
= 25°C
T
A
= 125°C
T
A
= -55°C
Test Voltage Values (Volts)
* ELECTRICAL CHARACTERISTICS
Each MECL 10K series circuit has been designed to meet
the dc specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs
are terminated through a 100
Ω
resistor to -2.0 volts.
SYMBOL
PARAMETER
TEST VOLTAGE APPLIED TO PINS BELOW:
Pinouts referenced are for F package, check Pin Assignments
V
CC
= 2.0V, Output Load = 100
Ω
to GND
Functional
Parameters:
V
IN
4, 7, 11, 13 2, 3, 14, 15
4, 7, 11, 13 2, 3, 14, 15
4, 7, 11, 13 2, 3, 14, 15
4, 7, 11, 13 2, 3, 14, 15
1, 16
1, 16
1, 16
1, 16
V
OUT
V
CC
1.0
1.0
1.0
1.0
4.0
1.0
3.5
ns
4.0
1.0
3.5
ns
4.4
1.0
3.9
ns
4.4
1.0
3.9
ns
8
8
8
8
UNITS
LIMITS
+125°C
-55°C
+25°C
Subgroup 9 Subgroup 10 Subgroup 11
MIN MAX MIN MAX MIN MAX
V
EEL
P.U.T.
2, 3 ,14, 15
2, 3 ,14, 15
2, 3 ,14, 15
2, 3 ,14, 15
t
TLH
Rise Time
1.1
3.3
t
THL
1.1
3.3
Austin Semiconductor, Inc.
4
t
PHL
1.0
2.9
Quad Line Receiver
Recei
eceiv
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
t
PLH
Fall Time
Propagation Delay
High to Low
Propagation Delay
Low to High
1.0
2.90
AS10515F16MIL
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