GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000
Revised December 2000
GTLP17T616
17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
flow and provides a buffered GTLP (CLKOUT) clock output
from the LVTTL CLKAB. The device provides a high speed
interface between cards operating at LVTTL logic levels
and a backplane operating at GTLP logic levels. High
speed backplane operation is a direct result of GTLP’s
reduced output swing (
<
1V), reduced input threshold levels
and output edge rate control. The edge rate control mini-
mizes bus settling time. GTLP is a Fairchild Semiconductor
derivative of the Gunning Transistor logic (GTL) JEDEC
standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port source/sink
−
24mA/
+
24mA
s
B Port sink
+
50mA
s
GTLP buffered CLKAB signal available (CLKOUT)
Ordering Code:
Order Number
GTLP17T616MEA
GTLP17T616MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS500327
www.fairchildsemi.com
GTLP17T616
Pin Descriptions
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
V
REF
CLKAB
CLKBA
A1–A17
B1–B17
CLKIN
CLKOUT
Description
A-to-B Output Enable
(Active LOW) (LVTTL levels)
B-to-A Output Enable
(Active LOW) (LVTTL levels)
A-to-B Clock/LE Enable
(Active LOW) (LVTTL levels)
B-to-A Clock/LE Enable
(Active LOW) (LVTTL levels)
A-to-B Latch Enable
(Transparent HIGH) (LVTTL levels)
B-to-A Latch Enable
(Transparent HIGH) (LVTTL levels)
GTLP Input Threshold
Reference Voltage
A-to-B Clock (LVTTL levels)
B-to-A Clock (LVTTL levels)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B Open Drain Outputs (GTLP Levels)
B-to-A Buffered Clock Output
(LVTTL levels)
GTLP Buffered Clock Input/Output of CLKAB
(GTLP Levels)
Connection Diagram
Truth Table
(Note 1)
Inputs
CEAB
X
L
L
X
X
L
L
OEAB
H
L
L
L
L
L
L
LEAB
X
L
L
H
H
L
L
CLKAB
X
H
L
X
X
A
X
X
X
L
H
L
H
Output
B
Z
B
0
(Note 2)
B
0
(Note 3)
L
H
L
H
Clocked
storage
of A data
H
L
L
X
X
B
0
(Note 3)
Clock inhibit
Latched
storage
of A data
Transparent
Mode
↑
↑
Note 1:
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2:
Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3:
Output level before the indicated steady-state input conditions were established.
www.fairchildsemi.com
2
GTLP17T616
Functional Description
The GTLP17T616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for
the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock
enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and
OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control the 17 bits
of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is low, the device operates on the
LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if
CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is
HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are
high impedance. The data flow of B-to-A is similar except that CEAB, OEBA, LEBA and CLKBA are used.
Logic Diagram
3
www.fairchildsemi.com
GTLP17T616
Absolute Maximum Ratings
(Note 4)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 5)
DC Output Sink Current into
A Port I
OL
DC Output Source Current from
A Port I
OH
DC Output Sink Current into
B Port in the LOW State, I
OL
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
ESD Rating
Storage Temperature (T
STG
)
100 mA
48 mA
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Recommended Operating
Conditions
Supply Voltage V
CC
/V
CCQ
Bus Termination Voltage (V
TT
)
GTLP
V
REF
Input Voltage (V
I
)
on A Port and Control Pins
on B Port
HIGH Level Output Current (I
OH
)
A Port
LOW Level Output Current (I
OL
)
A Port
0.0V to V
CC
0.0V to V
CC
1.47V to 1.53V
0.98V to 1.02V
3.15V to 3.45V
−
48 mA
−
24 mA
+
24 mA
+
50 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
>
2000V
−
65
°
C to
+
150
°
C
B Port
Operating Temperature (T
A
)
Note 4:
Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.
Note 5:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Symbol
V
IH
V
IL
V
REF
V
TT
V
IK
V
OH
A Port
B Port
Others
B Port
Others
B Port
B Port
V
TT
>
V
REF
+
50 mV
V
TT
>
V
REF
+
50 mV
V
CC
=
3.15V
V
CC
=
Min to Max (Note 7)
V
CC
=
3.15V
V
OL
A Port
B Port
I
I
Control Pins
A Port
B Port
I
PU/PD
I
OFF
I
I(hold)
I
OZH
I
OZL
I
CC
(V
CC
/V
CCQ
)
∆I
CC
(Note 8)
A Port and
Control Pins
All Ports
All Ports
A Port
A Port
B Port
A Port
B Port
A or B Ports
V
CC
=
3.45V
I
O
=
0
V
I
=
V
CC
or GND
V
CC
=
3.45V,
A or Control Inputs at V
CC
or GND
V
CC
=
3.45V
V
CC
=
Min to Max (Note 7)
V
CC
=
3.15V
V
CC
=
3.15V
V
CC
=
Min to Max (Note 7)
V
CC
=
3.45V
V
CC
=
3.45V
V
CC
=
0 to 1.5V
V
CC
=
0
V
CC
=
3.15V
V
CC
=
3.45V
I
I
= −18
mA
I
OH
= −100 µA
I
OH
= −18
mA
I
OH
= -24mA
I
OL
=
100
µA
I
OL
=
24mA
I
OL
=
40 mA
I
OL
=
50 mA
V
I
=
3.45V or 0V
V
I
=
3.45V or 0V
V
I
=
0 to 3.45V
V
I
/V
O
=
0 to 3.45V
V
I
or V
O
=
0 to 3.45V
V
I
=
0.8V
V
I
=
2.0V
V
O
=
3.45V
V
O
=
1.5V
V
O
=
0V
V
O
=
0.55V
Outputs HIGH
Outputs LOW
Outputs Disabled
One Input at 2.7V
0
75
−75
10
5
−10
−5
45
45
45
2
mA
mA
V
CC
–0.2
2.4
2.2
0.2
0.5
0.4
0.55
±5
±10
±5
±30
30
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
0.25
V
REF
+
50 mV
1.0
1.5
Test Conditions
Min
V
REF
+
0.05
2.0
0.0
V
REF
−
0.05
0.8
V
CC
−
1.2V
V
CC
−1.2
V
Typ
(Note 6)
V
TT
V
V
V
Max
Units
www.fairchildsemi.com
4
GTLP17T616
DC Electrical Characteristics
Symbol
C
i
Control Pins
A Port
B Port
(Continued)
Min
Typ
(Note 6)
5.0
7.0
9.0
pF
Max
Units
Test Conditions
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
Note 6:
All typical values are at V
CC
=
3.3V, V
CCQ
=
3.3V, and T
A
=
25°C.
Note 7:
For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 8:
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
Symbol
f
TOGGLE
f
MAX
t
WIDTH
t
SU
Maximum Toggle Frequency
Maximum Clock Frequency
Pulse Duration
Setup Time
Test Conditions
Transparent Mode
Registered Mode
LEAB or LEBA HIGH
CLKAB or CLKBA HIGH or LOW
A before CLKAB↑
B before CLKBA↑
A before LEAB↑
B before LEBA↑
CEAB before CLKAB↑
CEBA before CLKBA↑
t
HOLD
Hold Time
A after CLKAB↑
B after CLKBA↑
A after LEAB↑
B after LEBA↑
CEAB after CLKAB↑
CEBA after CLKBA↑
Min
125
125
3.0
3.0
0.6
1.2
0.5
1.3
1.4
1.2
0
0.2
0.2
0
0.5
0.6
ns
ns
Max
Unit
MHz
ns
5
www.fairchildsemi.com
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
