Integrated
Circuit
Systems, Inc.
Product Data Sheet
M901-01
VCSO B
ASED
C
LOCK
G
ENERATOR
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
XTAL_2
GND
VCC
XTAL_1 / REF_IN
NC
VCC
NC
NC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that uses an internal
VCSO (Voltage Controlled SAW
Oscillator) to produce a very low
jitter output clock. The output clock
(e.g., frequencies of
622.08
,
311.04
,
155.52
, or
77.76
MHz with the
M901-01-622.0800
) is provided from a
LVPECL clock output pair. Output frequency accuracy
is assured by phase-locking the VCSO to an external
input reference frequency (e.g., frequencies of
19.44
,
38.80
,
77.76
, or
155.52
MHz with the
M901-01-622.0800
).
The input reference can either be an external crystal,
utilizing the internal crystal oscillator, or a stable
external clock source such as a packaged crystal
oscillator.
M0
M2
M3
M4
M5
VCC
DNC
DNC
DNC
28
29
30
31
32
33
34
35
36
M901-01
(Top View)
18
17
16
15
14
13
12
11
10
NC
OUT_EN
nFOUT
FOUT
GND
P1
P0
VCC
GND
F
EATURES
◆
Output clock frequency from 62MHz to 700MHz
(Consult factory for VCSO frequency availability)
◆
Low jitter 0.5ps rms, typ. (12kHz-20MHz @622.08MHz)
◆
Ideal for OC-48 (STM-16), Gigabit Ethernet clock ref
◆
Integrated SAW (surface acoustic wave) delay line
◆
XTAL or LVCMOS reference input
◆
LVPECL output
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
25.00
Figure 1: Pin Assignment
Example Output Frequency Configurations
*
Ref Clock
Freq
(MHz)
19.44
VCSO
Freq
1
(MHz)
622.08
625.00
Output
Freq
(MHz)
622.08
155.52
156.25
Application
OC-12/48
(STM-4/16)
10GbE
Table 1: Example Output Frequency Configurations *
Note1: Specify VCSO center frequency at time of order
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M901-01
XTAL_1 / REF_IN
XTAL_2
Phase
Detector
OP_IN
nOP_IN
R
IN
SAW Delay Line
XTAL
OSC
R
IN
Loop Filter
Amplifier
Phase
Shifter
VCSO
M Divider
M1=0
P Divider
FOUT
nFOUT
5
M5:2, M 0
Figure 2: Block Diagram
Note *: Other frequencies available. See “Ordering Information” on pg. 8.
M901-01 Datasheet Rev 4.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
2
P1:0
OUT_EN
1
2
3
4
5
6
7
8
9
Revised 30Jul2004
Networking & Communications
●
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Integrated
Circuit
Systems, Inc.
M901-01
VCSO B
ASED
C
LOCK
G
ENERATOR
Product Data Sheet
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 22, 25, 33
12
13
15
16
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
P0
P1
FOUT
nFOUT
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Input
Output
Power supply ground connections.
External loop filter connections. See Figure 4,
External Loop Filter, on pg. 4.
Power supply connection, connect to +
3.3
V.
P divider (output divider) inputs
P1
:
0
.
Internal pull-down resistor
1
LVCMOS/LVTTL. See 4, Pin Selection of P Divider
Using P1:0 Pins, on pg. 2.
No internal terminator
Clock output pair. Differential LVPECL.
17
OUT_EN
Input
18, 20, 21, 23
24
27
28
29
30
31
32
19, 34, 35, 36
NC
XTAL_1 / REF_IN
XTAL_2
M0
M2
M3
M4
M5
DNC
Input
Input
Output Enable:
Logic
1
resets M and P dividers and forces
Internal pull-down resistor
1
FOUT
to LOW and
nFOUT
to HIGH.
Logic
0
enables the outputs.
LVCMOS/LVTTL.
No connection.
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
External crystal connection. Leave unconnected
when driving pin
27
with external clock reference.
Internal pull-down resistor
1
M divider (feedback divider) inputs
M5
:
2, and M0
.
See Table 3, Example Pin Selection of M Divider
Using M5:2, M0 Pins, on pg. 2.
Internal pull-up resistor
1
Do Not Connect.
Table 2: Pin Descriptions
Input
Note1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 6.
D
EVICE
C
ONFIGURATION
T
ABLES
Example Pin Selection of M Divider Using
M5:2, M0
Pins
Input Clock Freq
M5:0
Pin
(MHz)
for Common
Settings
VCSO Freqs
Definition
(
Pins 32-28
)
F
VCSO
=
F
VCSO
=
1
M5 -M2, M0
622.08
625.00
2
5
3
4 3 2
1
4
0
Feedback Divider Value “M”
0 0010 0
0 0100 0
0 1000 0
0 1100 1
1 0000 0
1 1110 1
M=4
M=
8
M =
16
M =
25
M =
32
M =
61
19.44
155.52
77.76
38.80
25.00
156.25
Note1:
Note2:
Note3:
Note4:
F
VCSO
= 622.08 MHz (e.g., M901-01-622.0800)
F
VCSO
= 625.00 MHz (e.g., M901-01-625.0000)
M5 pin has pull-up resister; M4-M2 and M0 have pull-down.
M1 bit is always 0 (no M1 pin exists).
Pin Selection of P Divider Using
P1:0
Pins
P1:0
Settings P Divider
Output Frequency (MHz)
Example when
(Pin 13 and 12) Value
F
VCSO
=
622.08
1
P1
P0
0
0
1
622.08
0
1
2
311.04
1
0
4
155.52
1
1
8
77.76
Table 4: Pin Selection of P Divider Using P1:0 Pins
Note1: F
VCSO
= 622.08MHz (e.g., M901-01-622.0800)
Table 3: Example Pin Selection of M Divider Using M5:2, M0 Pins
M901-01 Datasheet Rev 4.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
2 of 8
Networking & Communications
●
Revised 30Jul2004
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●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M901-01
VCSO B
ASED
C
LOCK
G
ENERATOR
Product Data Sheet
P Divider and Outputs
The M901-01 provides one differential LVPECL output
pair:
FOUT, nFOUT.
By using the P divider, the output
frequency can be the VCSO center frequency (Fvcso)
or 1/2, 1/4, or 1/8 Fvcso.
The
P1
and
P0
pins select the value for the P divider.
See Table 4, Pin Selection of P Divider Using P1:0
Pins, on pg. 2.
F
UNCTIONAL
D
ESCRIPTION
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to an input reference clock. The M901-01
combines the flexibility of a VCSO (Voltage Controlled
SAW Oscillator) with the stability of a crystal oscillator.
The M901-01 uses a high-Q, narrow tuning range
VCSO with a center frequency that is specified at time
of device order (see Ordering Information on pg. 8).
A suitable reference clock frequency, M Divider setting,
and loop filter configuration must be used to assure
proper operation.
Input Reference
An input clock reference is required. It should be a
stable external clock source, such as a packaged
crystal oscillator or distributed system clock. The clock
reference is applied to the
REF_IN
input pin, which is
internally applied to the non-inverting input of the phase
detector.
See External Crystal Specifications in Application
Information on pg. 4.
When the P divider is included, the complete
relationship for the output frequency is defined as:
M
-
Fvcso = Fref_in
×
----
P
Configuration of M and P Dividers
The M and P dividers can be set by pin configuration
using the input pins
M0, M2 - M5
,
P0
, and
P1
. The data on
pins
M5:2
and
M0
and on pins
P1:0
is passed directly to the
M and P dividers.
The divider configuration of the M901-01 is reset and
the outputs disabled when the input pin
OUT_EN
is set
HIGH.
MR
is set LOW for divider configuration to be
operational.
Internal PLL Operation
The internal PLL is comprised of a first order, type 3
frequency/phase detector, a SAW delay-line based
VCO (VCSO), and a clock feedback divider.
The clock feedback divider (M Divider) divides the
VCSO frequency and drives the inverting input of the
phase detector, which is compared to the input
reference clock. The PLL is “locked” when the phase
detector inputs are aligned in frequency and phase; the
phase detector output controls the VCSO frequency to
achieve this, and the external loop filter provides
stability to this frequency (and phase) control system.
Hence, the VCSO frequency operates at “M” times the
input reference frequency, thus accomplishing
frequency translation. The external loop filter also acts
as a low pass filter that provides attenuation of clock
jitter on the reference input.
The relationship between the VCSO output frequency,
the M divider, and the input reference frequency is
defined as follows:
Fvcso = Fref_in
×
M
The product of M and the input frequency must be such
that it falls within the “lock” range of the VCSO.
See APR in AC Characteristics on pg. 6.
M901-01 Datasheet Rev 4.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
3 of 8
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Revised 30Jul2004
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tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M901-01
VCSO B
ASED
C
LOCK
G
ENERATOR
Product Data Sheet
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
4
9
A
PPLICATION
I
NFORMATION
This section includes information on the optional
external crystal and on the external loop filter.
The subsections on the loop filter provide example
component values and also briefly describe the SAW
PLL simulator tool and additional application
information available at
www.icst.com.
External Crystal Specifications
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should have the following general specifications:
Crystal Specifications
Parameter
Min Typ Max Unit
AT-cut quartz
Fundamental
16
40
50
C
LOOP
OP_OUT
8
5
R
POST
nOP_OUT
nVC
6
7
nOP_IN
VC
Figure 4: External Loop Filter
Example External Loop Filter Component Values
PLL
Damping
Bandwidth Factor
R loop
1.5
kΩ
4.7
kΩ
10.0
kΩ
C loop
4.70
µF
1.00
µF
1.00
µF
R post C post
50
kΩ
50
kΩ
50
kΩ
3300
pF
1500
pF
470
pF
470
pF
f
0
ESR
Crystal Type
Mode of Oscillation
Frequency Range
MHz
400
Hz
1.2
kHz
2.5
kHz
9.9
kHz
2.0
2.9
6.2
3.6
Equivalent Series Resistance
Spurious Response (non-harmonic)
Load Capacitance,
parallel load resonant
Drive Level
16
0.1
Ω
-
40
dBc
pF
mW
C
L
P
0
32
1.0
39.0
kΩ
0.022
µF
20
kΩ
Table 6: Example External Loop Filter Component Values
PLL Simulator Tool Available
A free PC software utility is available on the ICS web
site. The SAW PLL Simulator is a downloadable
application that simulates PLL jitter and wander transfer
characteristics. This enables the user to set appropriate
external loop component values in a given application.
Refer to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
for additional information.
Table 5: Crystal Specifications
The external crystal will be applied to the
XTAL_1 / REF_IN
and
XTAL_2
input pins. External crystal load capacitors
are also required.
Recommended External Crystal Configuration
M901-01
M9xx-0x
XTAL_1 / REF_IN
C1
XTAL
XTAL_2
C2
XTAL OSC
SAW PLL Application Notes Available
The ICS web site (www.icst.com) also has application
notes on:
Figure 3: Recommended External Crystal Configuration
•
PCB layout guidelines (including special detailed
•
•
•
instructions for preventing issues such as external
reference crosstalk)
Any new special device application details that may
become available
Instructions for using PLL simulator software
Guidelines for PCB fabrication (including recom-
mended PCB footprint, solder mask, and furnace
profile)
Refer to the SAW PLL Application Notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes and any additional product
information that may become available.
XTAL Load Capacitance Specification = 18 pF
C1 = 27 pF
C2 = 33 pF
External load capacitors C1 and C2 present a load of 15 pf
to the crystal (they are seen in series by the crystal through
the common ground connection). With the additional of PCB
trace capacitance and M901-01 input capacitance, the total
load to the crystal is about 18 pf.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M901-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
M901-01 Datasheet Rev 4.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
4 of 8
Networking & Communications
●
Revised 30Jul2004
w w w. i c s t . c o m
●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M901-01
VCSO B
ASED
C
LOCK
G
ENERATOR
Product Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS1
Symbol Parameter
Rating
Unit
V
I
V
O
V
CC
T
S
Inputs
Outputs
Power Supply Voltage
Storage Temperature
-
0.5
to V
CC
+
0.5
-
0.5
to V
CC
+
0.5
4.6
V
V
V
o
C
-
45
to +
100
Table 7: Absolute Maximum Ratings
Note1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
R
ECOMMENDED
C
ONDITIONS OF
O
PERATION
Symbol Parameter
Min
3.135
Typ
3.3
Max
3.465
Unit
V
CC
T
A
Positive Supply Voltage
Ambient Operating Temperature
Commercial
Industrial
V
o
C
o
C
0
-40
+
70
+
85
Table 8: Recommended Conditions of Operation
M901-01 Datasheet Rev 4.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
5 of 8
Networking & Communications
●
Revised 30Jul2004
w w w. i c s t . c o m
●
tel (508) 852-5400
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