19-4503; Rev 0; 4/09
3-Channel, Low-Leakage ESD Protector
General Description
The MAX14541E low-capacitance
Q15kV
ESD-protection
diode array is designed to protect sensitive electronics
attached to communication lines. Each channel consists
of a pair of diodes that steer ESD current pulses to V
CC
or GND.
The MAX14541E protects against ESD pulses up to
Q15kV
Human Body Model (HBM) and
Q15kV
Air-Gap
Discharge, as specified in IEC 61000-4-2. The device
has a 6pF (typ) on-capacitance per channel, making
them ideal for use on high-speed data I/O interfaces.
The MAX14541E is a triple I/O protector designed for
biometric connectors, portable connectors, and SVGA
video connections with ultra-low leakage current.
The device is available in a 5-pin SC70 package and is
specified over the -40NC to +125NC automotive operating
temperature range.
±15kV Human Body Model
±15kV IEC 61000-4-2 Air-Gap Discharge
±8kV IEC 61000-4-2 Contact Discharge
S
6pF (typ) Low Input Capacitance
S
1nA (max) Low-Leakage Current
S
+0.9V to +16V Supply Voltage Range
S
5-Pin SC70 (2.0mm x 2.2mm) Package
Features
S
High-Speed Data Line ESD Protection
MAX14541E
Ordering Information
PART
MAX14541EAXK+T
T = Tape and reel.
TEMP
RANGE
-40NC to +125NC
PIN-
PACKAGE
5 SC70
TOP
MARK
ATY
Applications
Glucose Meters
MP3 Players
Digital Cameras
Handheld Equipment
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
V
CC
GND
I/O-1
1
2
3
+
5
MAX14541E
4
I/O-2
I/O-3
SC70
_______________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
3-Channel, Low-Leakage ESD Protector
MAX14541E
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
V
CC
to GND...........................................................-0.3V to +18V
I/O-1, I/O-2, I/O-3 to GND ........................ -0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70NC)
5-Pin SC70 (derate 3.1mW/NC above +70NC) .........246.9mW
Thermal Resistance (Note 1)
B
JA
.............................................................................324NC/W
B
JC
............................................................................115NC/W
Operating Temperature Range ........................ -40NC to +125NC
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature .....................................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Supply Current
Diode Forward Voltage
SYMBOL
V
CC
I
CC
V
F
(V
CC
= +5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
CONDITIONS
MIN
0.9
1
I
F
= 10mA, T
A
= +25°C
T
A
= +25°C, ±15kV
Human Body Model,
I
F
= 10A
T
A
= +25°C, ±8kV
Contact Discharge
(IEC 61000-4-2),
I
F
= 24A
T
A
= +25°C, ±15kV
Air-Gap Discharge
(IEC 61000-4-2),
I
F
= 45A
Channel Leakage Current
(Note 4)
I/O Capacitance
ESD PROTECTION
Human Body Model
IEC 61000-4-2 Air-Gap
Discharge
IEC 61000-4-2 Contact
Discharge
±15
±15
±8
kV
kV
kV
T
A
= -40°C to +50°C
T
A
= -40°C to +125°C
Bias of V
CC
/2, f = 1MHz (Note 4)
Positive transients
Negative transients
Positive transients
Negative transients
Positive transients
Negative transients
-1
-1
6
0.65
TYP
MAX
16
100
0.95
V
CC
+
25
-25
V
CC
+
60
-60
V
CC
+
100
-100
+1
+1
7
V
V
nA
µA
pF
UNITS
V
nA
V
V
Channel Clamp Voltage
(Note 3)
V
C
V
Note 2:
Parameters are 100% production tested at TA = +25°C. Specifications over temperature guaranteed by design only.
Note 3:
Idealized clamp voltages. See the
Applications Information
section for more information.
Note 4:
Guaranteed by design, not production tested.
2
______________________________________________________________________________________
3-Channel, Low-Leakage ESD Protector
Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25NC, unless otherwise noted.)
MAX14541E
SUPPLY CURRENT
vs. TEMPERATURE
MAX14541E toc01
CLAMP VOLTAGE
vs. DC CURRENT
MAX14541E toc02
I/O LEAKAGE CURRENT
vs. TEMPERATURE
MAX14541E toc03
100
10
SUPPLY CURRENT (nA)
1
0.1
V
CC
= 5V
0.01
0.001
V
CC
= 3.3V
V
CC
= 12V
1.1
10
I/O LEAKAGE CURRENT (nA)
CLAMP VOLTAGE (V)
1.0
I/O TO V
CC
1
0.9
I/O TO GND
0.1
V
CC
= 12V
0.8
0.01
V
CC
= 5V
V
CC
= 3.3V
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (
o
C)
0.7
10
30
50
70
90 110
DC CURRENT (mA)
130
150
0.001
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (
o
C)
INPUT CAPACITANCE
vs. INPUT VOLTAGE
MAX14541E toc04
INPUT CAPACITANCE
vs. INPUT VOLTAGE
V
CC
= 12V
INPUT CAPACITANCE (pF)
8
6
4
2
0
MAX14541E toc05
10
8
6
V
CC
= 5V
4
2
0
0
1
2
3
INPUT VOLTAGE (V)
4
V
CC
= 3.3V
10
INPUT CAPACITANCE (pF)
5
0
2
4
6
8
INPUT VOLTAGE (V)
10
12
_______________________________________________________________________________________
3
3-Channel, Low-Leakage ESD Protector
MAX14541E
_______________________________________________________________Pin Description
PIN
1
2
3
4
5
NAME
V
CC
GND
I/O-1
I/O-2
I/O-3
FUNCTION
Power-Supply Input. Bypass V
CC
to GND with a 0.1FF ceramic capacitor as close as possible to
the device.
Ground. Connect GND with a low-impedance connection to the ground plane.
ESD-Protected Channel
ESD-Protected Channel
ESD-Protected Channel
__________________________________________________________Functional Diagram
MAX14541E
V
CC
I/O-1
I/O-2
I/O-3
GND
4
______________________________________________________________________________________
3-Channel, Low-Leakage ESD Protector
________________Detailed Description
The MAX14541E low-leakage, low-capacitance,
Q15kV
ESD-protection diode arrays are suitable for high-speed
and general-signal ESD protection. Low input capaci-
tance makes this device ideal for ESD protection of
high-speed signals. Each channel consists of a pair of
diodes that steer ESD current pulses to V
CC
or GND. The
MAX14541E is a 3-channel device (see the
Functional
Diagram).
The MAX14541E is designed to work in conjunction with
a device’s intrinsic ESD protection. The MAX14541E
limits the excursion of the ESD event to below
Q25V
peak voltage when subjected to the Human Body Model
waveform. When subjected to the IEC 61000-4-2 Contact
Discharge waveform, the peak voltage is limited to
Q60V.
The peak voltage is limited to
Q100V
when sub-
jected to Air-Gap Discharge. The device protected by
the MAX14541E must be able to withstand these peak
voltages, plus any additional voltage generated by the
parasitic of the board.
where I
ESD
is the ESD current pulse.
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 2). For example,
in a +15kV IEC 61000-4-7 Air-Gap Discharge ESD event,
the pulse current rises to approximately 45A in 1ns
(di/dt = 45 x 10
9
). An inductance of only 10nH adds an
additional 450V to the clamp voltage, and represents
approximately 0.5in of board trace. Regardless of the
device’s specified diode clamp voltage, a poor layout
with parasitic inductance significantly increases the
effective clamp voltage at the protected signal line.
Minimize the effects of parasitic inductance by placing
the MAX14541E as close as possible to the connector
(or ESD contact point).
A low-ESR 0.1FF capacitor is required between V
CC
and
GND to get the maximum ESD protection possible. This
bypass capacitor absorbs the charge transferred by a
positive ESD event. Ideally, the supply rail (V
CC
) would
absorb the charge caused by a positive ESD strike
without changing its regulated value. All power supplies
have an effective output impedance on their positive
rails. If a power supply’s effective output impedance is
1I, then by using V = I x R, the clamping voltage of V
C
increases by the equation V
C
= I
ESD
x R
OUT
. A +8kV IEC
61000-4-2 ESD event generates a current spike of 24A.
The clamping voltage increases by V
C
= 24A x 1I, or
V
C
= 24V. Again, a poor layout without proper bypassing
increases the clamping voltage. A ceramic chip capaci-
tor mounted as close as possible to the MAX14541E
V
CC
pin is the best choice for this application. A bypass
capacitor should also be placed as close as possible to
the protected device.
POSITIVE SUPPLY RAIL
MAX14541E
___________Applications Information
Maximum protection against ESD damage results from
proper board layout (see the
Layout Recommendations
section). A good layout reduces the parasitic series
inductance on the ground line, supply line, and protect-
ed signal lines. The MAX14541E ESD diodes clamp the
voltage on the protected lines during an ESD event and
shunt the current to GND or V
CC
. In an ideal circuit, the
clamping voltage (V
C
) is defined as the forward voltage
drop (V
F
) of the protection diode, plus any supply volt-
age present on the cathode.
For positive ESD pulses:
V
C
= V
CC
+ V
F
For negative ESD pulses:
V
C
= -V
F
The effect of the parasitic series inductance on the lines
must also be considered (Figure 1).
For positive ESD pulses:
Design Considerations
L2
D1
L1
PROTECTED
LINE
I/O_
D2
d
(
I
)
d(I )
V
C
=
V
CC
+
V
F(D1)
+
L1
×
ESD
+
L2
×
ESD
dt
dt
For negative ESD pulses:
d(I
)
d(I
)
V
C
= −
V
F(D2)
+
L1
×
ESD
+
L3
×
ESD
dt
dt
L3
GROUND RAIL
Figure 1. Parasitic Series Inductance
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5
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