CY28RS400
Clock Generator for ATI
®
RS400 Chipset
Features
• Supports Intel CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 48 MHz USB clock
• 33 MHz PCI clock
CPU
x3
SRC
x8
PCI
x1
REF
x3
USB_48
x1
• Low-voltage frequency select input
®
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
FS_[C:A]
VTT_PWRGD#
IREF
Pin Configuration
VDD_REF
REF[0:2]
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
PD
PLL2
SDATA
SCLK
I
2
C
Logic
Xin
XOUT
VDD_48
VDD_CPU
USB_48
CPUT[0:2], CPUC[0:2],
VSS_48
VDD_SRC
VTT_PWRGD#/PD
SRCT[0:5],SRCC[0:5]
SCLK
SDATA
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
FSC
CLKREQ#0
VDD_PCI
CLKREQ#1
PCI
SRCT5
SRCC5
VDD_SRC
VSS_SRC
VDD_48 MHz
SRCT4
SRCC4
SRCT3
USB_48
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0/FSA
REF1/FSB
REF2
VDD_PCI
PCI0/409_410
VSS_PCI
CPU_STOP#
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
CPUT2
CPUC2
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
56 SSOP/TSSOP
CY28RS400
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
CY28RS400
Pin Description
Pin No.
47,46,43,42,
41,40
50
Name
CPUT/C[2:0]
PCI0/409_410
Type
O, DIF Differential CPU clock output.
Intel Type-X buffer.
I/O,
PD
33 MHz clock output/CPU Frequency table Select
Intel Type-5 buffer.
0 = 410 frequency select table
1 = 409 frequency select table.
This has an internal pull-down
A precision resistor attached to this pin is connected to the internal current reference.
Description
37
54
53
52
7
8
27, 28, 30, 29
12, 13, 16,
17, 18, 19,
22, 23, 24, 25
,34,33
10,11
IREF
REF0/ FSA
REF1/FSB
REF2
SCLK
SDATA
SRCST/C[1:0]
SRCT/C[5:0]
I
I/O, SE, 14.318 MHz REF clock ouput/ CPU Frequency Select. Intel
®
Type-5 buffer.
I/O, SE 14.318 MHz REF clock ouput
/ CPU Frequency Select.
Intel Type-5 buffer.
O, SE 14.318 MHz REF clock ouput. Intel Type-5 buffer.
I,PU
SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down.
I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down.
O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock
support through SMBUS
O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer.
CLKREQ#[0:1]
I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard
PD specification. These pins have an internal pull-down.
0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled
O, SE 48 MHz clock output. Intel Type-3A buffer.
I
PD
I, PU
I
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
I
O
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin
becomes a realtime input for asserting power down (active high)
3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned
off two cycles after assertion of this pin
3.3V LVTTL input. CPU Clock Frequency Select
3.3V power supply for USB outputs
3.3V power supply for CPU outputs
3.3V power supply for PCI outputs
3.3V power supply for REF outputs
3.3V power supply for SRC outputs
3.3V power supply for SRC outputs
3.3V power supply for SRCS outputs
3.3V Analog Power for PLLs
Ground for USB outputs
Ground for CPU outputs
Ground for PCI outputs
Ground for REF outputs
Ground for SRC outputs
Ground for SRC outputs
Ground for SRCS outputs
Analog Ground
14.318 MHz Crystal Input
14.318 MHz Crystal Output
4
6
USB_48
VTT_PWRGD#/PD
48
9
3
45
51
56
14, 21
35
32
39
5
44
49
55
15, 20, 26
36
31
38
1
2
CPU_STP#
FSC
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDD_SRC1
VDD_SRCS
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSS_SRC1
VSS_SRCS
VSSA
XIN
XOUT
Rev 1.0, November 22, 2006
Page 2 of 18
CY28RS400
Frequency Select Pins (FS_A, FS_B, FS_C and
409_410)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C and 409_410
inputs prior to VTT_PWRGD# assertion (as seen by the clock
synthesizer). Upon VTT_PWRGD# being sampled low by the
clock chip (indicating processor VTT voltage is stable), the
clock chip samples the FS_A, FS_B, FS_C and 409_410 input
values. For all logic levels of FS_A, FS_B, FS_C and 409_410
VTT_PWRGD# employs a one-shot functionality in that once
a valid low on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C and 409-410 transitions
will be ignored. There are 2 CPU frequency select tables. One
based on the CK409 specifications and one based on the
CK410 specifications. The table to be used is determined by
the value latched on the PCI0/409_410 pin by the
VTT_PWRGD/PD# pin. A '0' on this pin selects the 410
frequency table and a '1' on this pin selects the 409 frequency
table. In the 409 table, only the FS_A and FS_B pins influence
the frequency selection.
Table 1. Frequency Select Table (FS_A FS_B FS_C) 410 mode, 409_410 = 0
FS_C
1
0
0
0
1
FS_B
0
0
1
0
1
FS_A
1
1
0
0
1
CPU
100 MHz
133 MHz
200 MHz
266 MHz
Reserved
SRC
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Table 2. Frequency Select Table (FS_A FS_B) 410 mode, 409_410 = 1
FS_B
0
0
1
FS_A
0
1
0
CPU
100 MHz
133 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
USB
48 MHz
48 MHz
48 MHz
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 3.
The block write and block read protocol is outlined in
Table 4
while
Table 5
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Description
Table 3. Command Code Definition
Bit
7
(6:5)
(4:0)
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
0 = Block read or block write operation, 1 = Byte read or byte write operation
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Description
Bit
1
8:2
9
10
18:11
19
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Block Read Protocol
Description
Rev 1.0, November 22, 2006
Page 3 of 18
CY28RS400
Table 4. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
27:20
28
36:29
37
45:38
46
....
....
....
....
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Description
Bit
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Block Read Protocol
Description
Rev 1.0, November 22, 2006
Page 4 of 18
CY28RS400
Control Registers
Byte 0:Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC [T/C]0
SRCS[T/C]1
SRCS[T/C]0
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
REF2
REF1
REF0
PCI0
USB_48
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
REF2 Output Enable
0 = Disable, 1 = Enable
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Description
Byte 2: Control Register 2
Bit
7
@Pup
1
Name
CPUT/C
SRCT/C
USB_48
PCI
Reserved
Reserved
CPU
SRC
Reserved
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
48MHz Output Drive Strength
0 = 1x, 1 = 2x
33MHz Output Drive Strength
0 = 1x, 1 = 2x
Reserved
Reserved
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Reserved
Description
6
5
4
3
2
1
1
1
0
1
0
1
Rev 1.0, November 22, 2006
Page 5 of 18
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