Datasheet> 器件分类 > 存储> 存储> HYMD512646B8J-J

文档预览

HYMD512646B8J-J: 产品描述DDR DRAM Module, 128MX64, 0.7ns, CMOS, DIMM-184; 产品类别存储存储; 文件大小1MB，共30页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

下载文档详细参数全文预览

HYMD512646B8J-J概述

DDR DRAM Module, 128MX64, 0.7ns, CMOS, DIMM-184

HYMD512646B8J-J规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	DIMM, DIMM184
针数	184
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.7 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	166 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N184
内存密度	8589934592 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	184
字数	134217728 words
字数代码	128000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128MX64
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM184
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.16 A
最大压摆率	4.04 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

184pin Unbuffered DDR SDRAM DIMMs based on 512Mb B ver.

This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil

TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based unbuffered DIMM series provide

a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange

and addition.

FEATURES

•

JEDEC Standard 184-pin dual in-line memory module

(DIMM)

Two ranks 128M x 72, 128M x 64 and One rank 64M

x 72, 64M x 64, 32M x 64 organization

2.6V

0.1V VDD and VDDQ Power supply for

DDR400, 2.5V

0.2V for DDR333 and below

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

133/166/200MHz

DLL aligns DQ and DQS transition with CK transition

Programmable CAS Latency: DDR266(2, 2.5 clock),

DDR333(2.5 clock), DDR400(3 clock)

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial Presence Detect (SPD) with EEPROM

Built with 512Mb DDR SDRAMs in 400 mil TSOP II

packages

Lead-free product listed for each configuration

(RoHS compliant)

ADDRESS TABLE

Organization

256MB

512MB

1GB

32M x 64

64M x 64

64M x 72

128M x 64

128M x 72

Ranks

SDRAMs

32Mb x 16

64Mb x 8

128Mb x 8

# of

DRAMs

# of row/bank/column Address

13(A0~A12)/2(BA0,BA1)/10(A0~A9)

13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)

Refresh

Method

8K / 64ms

PERFORMANCE RANGE

Part-Number Suffix

Speed Bin

CL - tRCD- tRP

CL=3

Max Clock

Frequency

CL=2.5

CL=2

-D43

DDR400B

3-3-3

200

166

133

-J

DDR333

2.5-3-3

166

133

-H

DDR266B

2.5-3-3

133

Unit

MHz

Note:

1. 2.6V

0.1V VDD and VDDQ Power supply for DDR400 and 2.5V

0.2V for DDR333 and below

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.1 / May. 2005

推荐资源

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多