IS66WVE204816BLL
Advanced Information
3.0V Core Async/Page PSRAM
Overview
The IS66WVE204816BLL is an integrated memory device containing 32Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 110 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial -40°C~85°C
Packages:
48-ball TFBGA, 48-pin TSOP-I
Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Rev.00B | February 2010
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- SRAM@issi.com
1
IS66WVE204816BLL
Advanced Information
General Description
PSRAM products are high-speed, CMOS pseudo-static random access memory developed
for low-power, portable applications. The 32Mb DRAM core device is organized
as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory
interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus, PSRAM products incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
A user-accessible configuration registers (CR) defines how the PSRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special attention has been focused on current consumption during self-refresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the CR.
A0~A20
Address
Decode Logic
2048K X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
Configuration Register
(CR)
CE#
WE#
OE#
LB#
UB#
ZZ#
Control
Logic
DQ0~DQ15
[ Functional Block Diagram]
Rev.00B | February 2010
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- SRAM@issi.com
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IS66WVE204816BLL
Advanced Information
48Ball TFBGA Ball Assignment
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB#
DQ8
DQ9
VSSQ
VDDQ
DQ14
DQ15
A18
OE#
UB#
DQ10
DQ11
DQ12
DQ13
A19
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
ZZ#
DQ0
DQ2
VDD
VSS
DQ6
DQ7
A20
[Top View]
(Ball Down)
Rev.00B | February 2010
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IS66WVE204816BLL
Advanced Information
48-pin TSOP-I (Top View)
DQ11
DQ3
DQ10
DQ2
VSSQ
OE#
VDDQ
DQ9
DQ1
DQ8
DQ0
A8
A9
A10
A11
UB#
A17
A18
A19
CE#
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ4
DQ12
ZZ#
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15
VSS
VDD
A16
A15
A14
A13
A12
LB#
NC
A20
A3
A2
A1
A0
WE#
Rev.00B | February 2010
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- SRAM@issi.com
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IS66WVE204816BLL
Advanced Information
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VDD
VDDQ
VSS
VSSQ
DQ0~DQ15
A0~A20
LB#
UB#
CE#
OE#
WE#
ZZ#
Type
Power Supply
Power Supply
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Description
Core Power supply (2.7V~3.6V)
I/O Power supply (2.7V~3.6V)
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
Data Inputs/Outputs (DQ0~DQ15)
Address Input(A0~A20)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
Write Enable
Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device
can enter one of two low-power modes ( DPD or PAR).
Rev.00B | February 2010
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- SRAM@issi.com
5
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