电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

IS61NLP25618-150TQ

产品描述ZBT SRAM, 256KX18, 3.8ns, CMOS, PQFP100, TQFP-100
产品类别存储    存储   
文件大小129KB,共21页
制造商Integrated Silicon Solution ( ISSI )
下载文档 详细参数 全文预览

IS61NLP25618-150TQ概述

ZBT SRAM, 256KX18, 3.8ns, CMOS, PQFP100, TQFP-100

IS61NLP25618-150TQ规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Integrated Silicon Solution ( ISSI )
零件包装代码QFP
包装说明TQFP-100
针数100
Reach Compliance Codecompliant
ECCN代码3A991.B.2.A
最长访问时间3.8 ns
其他特性PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)150 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度4718592 bit
内存集成电路类型ZBT SRAM
内存宽度18
功能数量1
端子数量100
字数262144 words
字数代码256000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织256KX18
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)240
电源2.5,3.3 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.01 A
最小待机电流3.14 V
最大压摆率0.305 mA
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度14 mm
Base Number Matches1

文档预览

下载PDF文档
IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
128K x 32, 128K x 36 and 256K x 18
PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining for TQFP
Power Down mode
Common data inputs and data outputs
CKE
pin to enable clock and suspend operation
JEDEC 100-pin TQFP and 119 PBGA packages
Single +3.3V power supply (± 5%)
NP Version: 3.3V I/O Supply Voltage
NLP Version: 2.5V I/O Supply Voltage
Industrial temperature available
ISSI
®
NOVEMBER 2002
DESCRIPTION
The 4 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-150
3.8
6.7
150
-133
4.2
7.5
133
-100
5
10
100
Units
ns
ns
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
11/21/02
1
GD32E231学习2:GPIO驱动OLED及TC0定时中断
我喜欢先弄个显示的东西,有了显示后续的定时,传感器数据的显示就比较方便了,手上有个全彩的OLED小屏一直在使用,是SPI口的,这次先用IO口来模拟,后续再修改为SPI,所以硬件连线上直接 ......
wudianjun2001 GD32 MCU
求助大家一个电源仿真方面的问题
大家在做电源仿真的时候,电流密度设置多少,铜皮,过孔走线又怎么确定呀?? ...
他们逼我做卧底 电源技术
智能家居安防一体化解决终端
611141 作品源码:https://download.eeworld.com.cn/detail/nmg/623873 作品演示视频: ecd3f0f94caf63afa06c92f57aae1a2e ...
full_stack 玄铁RISC-V活动专区
关于RESERVED_BOOT_BLOCKS的问题,eboot大小256K ,为何只占10块?
问题是这样的,eboot运行起来之后我使用 F) Low-level format the Smart Media card 这时候可以看到DNW打印如下信息 Enter your selection: f Reserving Blocks ... ...reserve complete. ......
xixilil 嵌入式系统
Low Power Methodology Manual - For System-on-Chip Design
这本《Low Power Methodology Manual》的受众可以涵盖IC架构师、数字前端设计、后端设计、Custom Design等等。虽然说低功耗技术最有用的还是从算法、架构(包括软件)等high level的方面去考虑 ......
arui1999 下载中心专版
教程:如何为BBB制作cape(或:如何在系统启动时自动加载dtbo)
本帖最后由 wytalfred 于 2014-3-22 00:11 编辑 一、引子 如果你买来BBB是为了搞跟硬件相关的项目,那你八成需要制作一个cape。cape是BBB官方的叫法,其实就是指BBB的软件和硬件外设。通 ......
wytalfred DSP 与 ARM 处理器

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 484  2815  1824  1705  1521  54  48  35  15  56 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved