®
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
DESCRIPTION:
Integrated Device Technology, Inc.
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
FEATURES:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST™ speed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (
EN
) and asynchronous
Clear input (
CLR
)
• I
OL
= 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (
EN
) and
Clear (
CLR
) – ideal for parity bus interfacing in high-perform-
ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (
OE
1
,
OE
2
,
OE
3
) to allow multiuser control of the
interface, e.g.,
CS
, DMA and RD/
WR
. They are ideal for use
as an output port requiring HIGH I
OL
/I
OH
.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
D
0
EN
D
N
IDT54/74FCT824
D
0
EN
D
N
CLR
D
CL
Q
D
CL
Q
CLR
D
CL
Q
D
CL
Q
CP Q
CP Q
CP Q
CP Q
CP
CP
OE
Y
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
OE
Y
N
2608 cnv* 01
Y
0
Y
N
2608 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4618/2
7.19
1
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT821 10-BIT REGISTER
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4 P24-1
5 D24-1
6 E24-1
&
7
8 SO24-2
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
CP
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
LOGIC SYMBOLS
INDEX
D
2
D
3
D
4
NC
D
5
D
6
D
7
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
20
10
19
11
1213 14 15 16 17 18
D
8
D
9
GND
NC
CP
Y
9
Y
8
4 3 2
10
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
D
D
CP
CP
OE
10
Q
Y
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
2608 cnv* 03
IDT54/74FCT823/824 9-BIT REGISTERS
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
1
2
3
4 P24-1
5 D24-1
6 SO24-2
&
7
8 E24-1
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
D
2
D
3
D
4
NC
D
5
D
6
D
7
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
4 3 2
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
INDEX
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
D
9
Q
CP EN CLR
D
9
Y
CP
EN
CLR
OE
DIP/SOIC/CERPACK
TOP VIEW
D
8
CLR
GND
NC
CP
EN
Y
8
LCC
TOP VIEW
2608 cnv* 04
IDT54/74FCT825 8-BIT REGISTER
OE
1
OE
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLR
GND
1
2
3
4 P24-1
5 D24-1
6 E24-1
&
7
8 SO24-2
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
OE
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
EN
CP
INDEX
D
0
OE
2
OE
1
NC
V
CC
OE
3
Y
0
D
D
1
D
2
D
3
NC
D
4
D
5
D
6
1 28 27 26
5
25
6
24
7
23
8
22
L28-1
9
21
10
20
11
19
1213 14 15 16 17 18
4 3 2
Y
1
Y
2
Y
3
NC
Y
4
Y
5
Y
6
8
Q
CP EN CLR
D
8
Y
CP
EN
CLR
OE
1
OE
2
OE
3
D
7
CLR
GND
NC
CP
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
EN
Y
7
2608 cnv* 05
7.19
2
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT SELECTOR GUIDE
Device
10-Bit
Non-inverting
Inverting
FUNCTION TABLE
(1)
IDT54/74FCT821/823/825
8-Bit
OE
CLR
9-Bit
54/74FCT824A/B/C
Inputs
EN
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
D
I
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Internal/
Outputs
Q
I
Y
I
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
2608 tbl 01
H
H
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
Function
High Z
Clear
Hold
Load
PIN DESCRIPTION
Name
D
I
CLR
I/O
I
I
Description
The D flip-flop data inputs.
For both inverting and non-inverting
registers, when the clear input is LOW
and
OE
is LOW, the Q
I
outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
The register three-state outputs.
Clock Enable. When the clock enable
is LOW, data on the D
I
input is
transferred to the Q
I
output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the Q
I
outputs do
not change state,
regardless of the data or clock input
transitions.
Output Control. When the
OE
input is
HIGH, the Y
I
outputs are in the high
impedance state. When the
OE
input is
LOW, the TRUE register data is
present at the Y
I
outputs.
2608 tbl 10
CP
I
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
↑
= LOW-to-HIGH
Transition, Z = High Impedance
Y
I ,
Y
I
EN
O
I
FUNCTION TABLE
(1)
IDT54/74FCT824
Inputs
OE
CLR
EN
D
I
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Internal/
Outputs
Q
I
Y
I
H
L
L
L
NC
NC
H
L
H
L
Z
Z
Z
L
Z
NC
Z
Z
H
L
H
H
H
L
H
L
H
H
L
L
H
H
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
Function
High Z
Clear
Hold
Load
OE
I
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
↑
= LOW-to-
HIGH Transition, Z = High Impedance
7.19
3
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
(2)
Terminal Voltage
–0.5 to +7.0
V
TERM
with Respect to
GND
(3)
Terminal Voltage
V
TERM
–0.5 to V
CC
with Respect to
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
–0.5 to V
CC
V
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
–55 to +125
–65 to +135
–65 to +150
0.5
120
°
C
°
C
°
C
W
mA
NOTE:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
NOTES:
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
OH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300
µ
A
I
OH
= –15mA MIL.
I
OH
= –24mA COM'L.
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300
µ
A
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–75
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
2608 tbl 06
Unit
V
V
µ
A
µ
A
V
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.19
4
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
Min.
—
—
V
IN
≥
V
HC
V
IN
≤
V
LC
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4.0
mA
—
2.2
6.0
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
4.0
7.8
(5)
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2608 tbl 07
7.19
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
