NJU8721
PRELIMINARY
CLASS D HEADPHONE AMPLIFIER FOR DIGITAL AUDIO
s
GENERAL DESCRIPTION
The
NJU8721
is the class D Headphone Amplifier
6
∆Σ
modulation adapted in. Digital Attenuator, Mute,
and De-emphasis are incorporated. Input signal is
digital, Output signal is PWM converting to analog
signal with simple LC Filter. The
NJU8721
providing
very high power efficiency with class D operation is
suitable for portable audio set and notebook
computer.
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PACKAGE OUTLINE
NJU8721V
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FEATURES
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PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
F0/DATA
F1/REQ
F2/SCK
MUTE
DIN
LRCK
BCK
MCK
V
SS
q
Stereo Headphone Power Amplifier
: 22mW+22mW
STBY
Sixth-order 32fs Over Sampling
∆Σ
& PWM
TEST
Internal 8fs Over Sampling Digital Filter
V
SSR
Sampling Frequency : 96kHz (Max.)
De-Emphasis
: 32kHz, 44.1kHz, 48kHz
OUTR
System Clock
: 256fs
V
DDR
Digital Function
V
DDL
: Attenuator 107step, LOG Curve
OUTL
: Mute
Audio Signal Data Input Format
V
SSL
: 16bit, 18bit
MODE
2
: I S, LSB Justified, MSB Justified
RST
Package
: SSOP20
s
BLOCK DIAGRAM
V
DD
V
SS
POWER ON
RESET CIRCUIT
RST
MCK
LRCK
BCK
DIN
MUTE
STBY
MODE
F0/DATA
F1/REQ
F2/SCK
SYNCHRONIZED
CIRCUIT
V
DDL
AUDIO
SERIAL DATA
INTERFACE
8×fs
OVER SAMPLING
DIGITAL FILTER
OUTL
32×fs 6th∆Σ
+
PWM
V
SSL
V
DDR
OUTR
V
SSR
SYSTEM
CONTROL
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NJU8721
s
TERMINAL DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
STBY
TEST
V
SSR
OUTR
V
DDR
V
DDL
OUTL
V
SSL
MODE
RST
V
SS
MCK
BCK
LRCK
DIN
MUTE
I/O
I
I
−
O
−
−
O
−
I
−
−
I
I
I
I
I
Function
Standby Control Terminal
Low : Standby ON
High : Standby OFF
Manufacturer Testing Terminal
This terminal usually connects GND.
Rch Power GND, 0V
Rch Output Terminal
Rch Power Supply, V
DD
to 5.0V
Lch Power Supply, V
DD
to 5.0V
Lch Output terminal
Lch Power GND, 0V
Selecting Control Mode Terminal
Low : Parallel Control Mode
High : Serial Control Mode
Reset Terminal
Low level signal inputted to this terminal initializes the system.
Digital GND, 0V
Master Clock Input Terminal
The 256×fs clock inputs this terminal.
Audio Serial Data Bit Clock Input Terminal
This clock must synchronize with MCK.
L/R Channel Clock Input Terminal
This clock must synchronize with MCK.
Audio Serial Data Input Terminal
Mute Control Terminal
Low : Mute ON
High : Mute OFF
MODE=”Low” : Audio Data Format Selection
MODE=”High” : Control Register Serial Data Sift Clock Input Terminal
Taking data in the control register synchronizes with
rise edge of SCK signal.
MODE=”Low” : Audio Data Format Selection
MODE=”High” : Control Register Serial Data Request Input Terminal
MODE=”Low” : Audio Data Format Selection
MODE=”High” : Control Register Serial Data Input Terminal
Digital Power Supply, 3.3V
17
F2/SCK
I
18
19
20
F1/REQ
F0/DATA
V
DD
I
I
−
s
INPUT TERMINAL STRUCTURE
V
DD
Input Terminal
V
SS
NJU8721 Inside Circuit
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NJU8721
s
FUNCTIONAL DESCRIPTION
(1) Signal Output
PWM signals output from OUTL and OUTR terminal. These signals transformed into analog signal by
2nd-order or over LC filter. Then the output driver power is supplied to V
DDL
, V
DDR
, V
SSL
, and V
SSR
by high
response power supply for supply voltage rejection as switching regulator. THD of output signal depends on
power supply stability.
(2) Master Clock
As the internal circuit operation clock, 256
×
fs clock inputs to the MCK terminal.
(3) Reset
Setting Low level the RST terminal for 3ms or over initializes the internal circuit. This reset signal is
synchronized with the internal circuit operation clock. Then, it is processed OR with internal power on reset
generation signal. This is the internal reset signal. This signal initializes the function setting registers. At this
condition, output-drivers output GND level. The reset equivalent circuit is shown as follows.
Internal Reset
RST
D
D
D
D
D
D
D
D
Power on Reset
CLK
(About 10kHz)
Figure 1. Reset Equivalent Circuit
-3-
NJU8721
(4) Stand by
Setting the STBY terminal Low level makes the
NJU8721
stand by. At this condition, setting digital audio
format, attenuation level, de-emphasis, and attenuator operation time are held. Then output terminals (OUTR,
OUTL) are high-impedance.
(5) Control Mode Set
A controll mode is chosen by setting the MODE terminal from 2 mode as follows;
MODE
0
1
Parallel
Serial
Control Method
Parallel
Serial
Function
Setting Audio Format
Three-wire serial control
Terminals
F0, F1, F2
DATA, REQ, SCK
: Digital Audio Format is set at F0, F1, and F2 terminals.
:
NJU8721
is controlled at DATA, REQ, and SCK terminals by 3-wire serial control.
This setting by MODE terminal sets function with F0/DATA, F1/REQ, and F2/SCK.
Refer to
(8-5)F0,F1,F2
about function of F0, F1, and F2.
Refer to
(8)Control Register
about function of DATA, REQ, and SCK terminal.
(6) Mute
The
NJU8721
is muted by setting the MUTE terminal Low level. Current value of attenuator output level
becomes -∞. Then, by setting this terminal high level, the
NJU8721
outputs same signal level before mute
operation.
MUTE
0
1
Attenuation Level
-∞
Set Point
MUTE
MCK
Attenuation Value
Set Value
-∞
Figure 2. Mute Timing
-∞
1024/fs
1024/fs
Set Value
-4-
NJU8721
(7) Digital Audio Signal Interface
(7-1) Input Data Format Selection
2
An Input Data Format is selected from I S, MSB Justified or LSB Justified, and a data length is chosen
16 bits or 18 bits.
(7-2) Input Timing
Digital audio signal data inputted to the DIN terminal is taken in the internal sift register with BCK rising
edge. This serial data is send as follows by sampling rate clock (fs) rising/falling edges which is inputted to
the LRCK terminal.
Data Format
2
IS
MSB Justified
LSB Justified
Rising Edge
Lch Input Register
Rch
Input Register
Rch
Input Register
Falling Edge
Rch Input Register
Lch
Input Register
Lch
Input Register
BCK and LRCK need to synchronize with MCK.
LRCK
BCK
DIN
Left Channel
Right Channel
15 14 13
1
0
2
15 14 13
1
0
Figure 3.1. 16bits I S Data Format
LRCK
BCK
DIN
15 14 13
Left Channel
Right Channel
1 0
15 14 13
1
0
Figure 3.2. 16 bits MSB Justified Data Format
LRCK
BCK
DIN
0
Right Channel
Left Channel
15 14
3
2
1
0
15 14
3
2
1
0
Figure 3.3. 16bits LSB Justified Data Format
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