Philips Semiconductors
Product specification
Digital Video Comb Filter (DCF)
SAA7152
FEATURES
•
Comb filter circuit for luminance and chrominance
separation
•
Applicable for standards
– PAL B/G, M and N
– PAL 4.43 (525 lines, 60 Hz)
– NTSC M and N
– NTSC 4.43 (50 and 60 Hz)
•
Luminance and chrominance bypasses with short delay
in case of no filtering
•
Line-locked system clock; CCIR-compatible
•
I
2
C-bus
controlled
GENERAL DESCRIPTION
The CMOS digital comb filter circuit is located between
video analog-to-digital converters and the video
multistandard decoder SAA7151B (not applicable for
SAA7191B). The two-dimensional filtering is only
appropriate for standard signals from a source with
constant phase relationship between subcarrier signal and
horizontal frequency. The comb-filter has to be switched
off for VTR-signals and for separate VBS and C signals. In
VCR and S-Video operation the luminance low-pass and
the chrominance bandpass parts can still be used for noise
reduction purposes. The processing delay is:
21
×
LL27 clocks in active mode, or
3
×
LL27 in short delay bypass mode (BYPS = 1)
QUICK REFERENCE DATA
SYMBOL
V
DD
I
P
V
i
V
o
LL27
T
amb
PARAMETER
supply voltage (pins 11, 34, 44)
total supply current
input levels
output levels
typical system clock frequency
operating ambient temperature range
−
MIN.
4.5
5.0
85
TYP.
MAX.
5.5
180
V
mA
UNIT
TTL-compatible
TTL-compatible
−
0
27
−
−
70
MHz
°C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
SAA7152
Note
1. SOT187-2; 1997 January 06.
44
PACKAGE
PINS
PIN POSITION
PLCC
MATERIAL
plastic
CODE
SOT187
(1)
August 1996
2
Philips Semiconductors
Product specification
Digital Video Comb Filter (DCF)
PINNING
SYMBOL
RESN
LL27
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
V
DD1
V
SS1
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
SP
AP
SDA
SCL
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
V
SS2
V
DD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ground 2 (0 V)
+5 V supply input 2
luminance (Y) output data bits 7 to 0
connected to ground (shift pin for testing)
connected to ground (action pin for testing)
I
2
C-bus data line
I
2
C-bus clock line
CVBS input data bits 0 to 7
+5 V supply input
ground 1 (0 V)
chrominance input data bits CIN0 to CIN7
PIN
reset input; active low
line-locked system clock input (27 MHz)
DESCRIPTION
SAA7152
August 1996
4