16Mx64 bits
PC100 SDRAM Unbuffered DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V651601 H-Series
DESCRIPTION
The Hyundai HYM71V651601 H-Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of
eight 16Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP
package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each
SDRAM are mounted on the PCB.
The HYM71V651601 H-Series are Dual In-line Memory Modules suitable for easy interchange and addition of
128Mbytes memory. The HYM71V651601 H-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth.
FEATURES
•
PC100MHz support
•
168pin SDRAM Unbuffered DIMM
•
Serial Presence Detect with EEPROM
•
1.375” (34.93mm) Height PCB with Single Sided
components
•
Single 3.3
±
0.3V power supply
•
All devices pins are compatible with LVTTL interface
•
Data mask function by DQM
•
SDRAM internal banks : four banks
•
Module bank : one physical bank
•
Auto refresh and self refresh
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
-. 1, 2, 4, 8 or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
•
Programmable /CAS Latency
-. 2, 3 Clocks
ORDERING INFORMATION
PART NO.
HYM71V651601TH-8
HYM71V651601TH-10P
HYM71V651601TH-10S
HYM71V651601LTH-8
HYM71V651601LTH-10P
HYM71V651601LTH-10S
MAX.
FREQUENCY
125MHz
100MHz
100MHz
4 Banks
125MHz
100MHz
100MHz
Low Power
4K
TSOP-II
Gold
Normal
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.99
©1999
Hyundai MicroElectronics
PC100 SDRAM Unbuffered DIMM
HYM71V651601 H-Series
PIN DESCRIPTION
PIN NAME
CK0~CK3
Clock Inputs
DESCRIPTION
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enables or disables all inputs except CK, CKE and DQM.
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA9
Auto-precharge flag : A10
/RAS define the operation.
Refer to the function truth table for details.
/CAS define the operation.
Refer to the function truth table for details.
/WE define the operation.
Refer to the function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pins
Power supply for internal circuits and input/output buffers
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address input
Write Protect for Serial Presence Detect on DIMM
No Connect or Don’ t Use
CKE0
/S0, /S2
BA0, BA1
Clock Enable
Chip Select
SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
DQM0~DQM7
DQ0~DQ63
VCC
VSS
SCL
SDA
SA0~SA2
WP
NC
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connect
Rev. 1.1/Dec.99
2
PC100 SDRAM Unbuffered DIMM
HYM71V651601 H-Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
1
2
3
4
5
6
7
8
9
10
NAME
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
85
86
87
88
89
90
91
92
93
94
BACK SIDE
PIN NO.
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
41
42
43
44
45
46
47
48
49
50
51
52
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC
NC
VSS
NC
NC
VCC
/CAS
DQM4
DQM5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
FRONT SIDE
PIN NO.
NAME
VCC
CK0
VSS
NC
/S2
DQM2
DQM3
NC
VCC
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VCC
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
BACK SIDE
PIN NO.
NAME
*CK1
NC
VSS
CKE0
NC
DQM6
DQM7
NC
VCC
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
SA0
SA1
SA2
VCC
Architecture Key
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC
NC
VSS
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VCC
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
Voltage Key
Note :
*. CK1, CK3 are connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.1/Dec.99
3
PC100 SDRAM Unbuffered DIMM
HYM71V651601 H-Series
BLOCK DIAGRAM
Note :
1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1, CK3 is 10pF.
Rev. 1.1/Dec.99
4
PC100 SDRAM Unbuffered DIMM
HYM71V651601 H-Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
–61
BYTE62
BYTE63
BYTE64
BYTE65
~71
BYTE72
FUNCTION
DESCRIBED
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random
Column Address
Burst Lengths Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
Superset Information (may be used in future)
SPD Revision
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
....Manufacturer JEDEC ID Code
2ns
1ns
2ns
1ns
8ns
6ns
-8
FUNCTION
-10P
128 Bytes
256 Bytes
SDRAM
12
10
1 Banks
64 Bits
-
LVTTL
10ns
6ns
None
15.625µs
/ Self Refresh Supported
x8
None
tCCD = 1 CLK
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
10ns
6ns
-
-
20ns
16ns
20ns
48ns
10ns
6ns
-
-
20ns
20ns
20ns
50ns
128MB
2ns
1ns
2ns
1ns
-
Intel SPD 1.2A
-
Hyundai JEDEC ID
Unused
HEI (Korea)
HEA (United States)
HEU (Europe)
F0h
2ns
1ns
2ns
1ns
20h
10h
20h
10h
12ns
6ns
-
-
20ns
20ns
20ns
50ns
A0h
60h
00h
00h
14h
10h
14h
30h
10ns
6ns
80h
60h
-10S
-8
VALUE
-10P
80h
08h
04h
0Ch
0Ah
01h
40h
00h
01h
A0h
60h
00h
80h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
14h
14h
32h
20h
20h
10h
20h
10h
00h
12h
16h
ADh
FFh
01h
02h
03h
36h
3, 8
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
2
A0h
60h
1
-10S
NOTE
Manufacturing Location
Rev. 1.1/Dec.99
5
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