Commercial/Industrial
PA7540 PEEL Array™
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (f
MAX
)
- Industrial grade available for 4.5 to 5.5V V
CC
and
-40 to +85 °C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
presets, clock polarity, and other features, making the
PA7540 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (f
MAX
) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). ICT and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
I/C LK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
1
2
3
4
5
6
7
8
9
10
11
12
I/C LK1
24
23
22
21
20
19
18
17
16
15
14
13
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C LK2
I/C LK1
I/C LK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C LK2
Figure 2. Block Diagram
2 Inp u t/
G lo b al C lo ck P in s
G lo b al
C e lls
2
I/C L K 1
I/O
I/O
I/O
I/O
G lo b a l C e lls
I/O C e lls
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L o g ic
Array
8 4 (4 2 X2 )
A rray Inp u ts
tru e an d
c om p le m en t
20
I/O
C e lls
(IO C )
B urie d
lo g ic
2 0 I/O P in s
S O IC
20
L og ic
C o ntro l
C e lls
(L C C )
D IP
I/O
I/O
VC C
VC C
VC C
I/O
I/O
I/O
I/O
I/O
A
B
C
D
NC
I/O
I/O
I/O
I/O
20
L og ic fun c tio n s
to I/O ce lls
4
I/O
I/O
I/O
NC
I/O
I/O
I/O
5
6
7
8
9
10
11
3
2
1
28 27 26
25
24
23
22
21
20
19
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
5
6
7
8
9
10
11
4
3
2
1 28 27 26
25
24
23
22
21
20
19
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
G ND
20
4 s um te rm s
4 p ro d uc t te rm s
fo r G lo b al C ells
8 0 su m term s
(fo ur p e r L C C )
2 0 L og ic C o ntro l C e lls
2 o u tp ut fu n ctio ns p e r ce ll
(4 0 total o utp ut fu n ctio ns p o ss ib le )
0 8 -1 4 -0 02 A
PA 7540
L o g ic C o n tro l C e lls
I/C L K 2
1 2 1 3 1 4 1 5 1 6 1 71 8
12 13 14 15 16 17 18
I/C LK2
I/C LK2
GND
GND
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P L C C -J
I/O
P L C C -J N
08-14-001B
1
04-02-051B
Commercial/Industrial
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7540 PEEL™ Array, 42 inputs are
available into the array from the I/O cells and input/global-
clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7540 PEEL™ Arrays contains 84 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can be
used for clocks, resets, presets and output enables instead of
just simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From G lobal C ell
S ys tem C lock
P reset
R egType R eset
From
IO C ells
(IO C) and
I/CLKs
42 Array Inputs
O n /O ff
MUX
From
Logic
Control
Cells
(LCC)
P
D ,T,J
Q
To
A rray
MUX
K
R EG
R
To
G lobal
Cells
84 Product Term s
From
A rray
A
B
C
D
MUX
To
I/O
C ell
To
Logic C ontrol
Cells
(LCC)
08 -14 -0 04 A
Figure 4. Logic Control Cell Block Diagram
P A 75 40 L ogic A rra y
84 Sum Term s
08-14-003A
Figure 3 PA7540 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
2
04-02-051B
Commercial/Industrial
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable
P
D R e g is te r
Q = D after clocked
can be registered, one output can be combinatorial and the
third, an output enable. The multi-function PEEL™ Array logic
cells are equivalent to two or three macrocells of other PLDs,
which have only one output per cell. They also allow registers
to be truly buried from I/O pins without limiting them to input-
only (see Figure 8 ).
From G lobal C ell
I/O C ell C lock
D
Q
B est for storage, simple coun ters,
shifters and state machines w ith
few hold (loop) conditions.
R
T
P
Q
T R e g is te r
Q toggles when T = 1
Q holds when T = 0
REG/
Latch
Q
R
B est for wide binary counters (saves
product terms) and state mac hines
with many hold (loop) conditio ns.
To
A rray
Input
MUX
J
P
Q
K
J K R e g is te r
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1
when J/K = 1/0
Q = 0
when J/K = 0/1
R
C ombines features of both D and T
registers.
08-14-005A
From
Logic
C ontrol
C ell
A ,B ,C
or
Q
MUX
I/O P in
MUX
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register or the output
enable for the connected I/O cell. Note that the sums
controlling clocks, resets, presets and output enables are
complete sum-of-product functions, not just product terms
as with most other PLDs. This also means that any input or
I/O pin can be used as a clock or other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 10).
D
1 0
7540 /O C ell (IO C )
08-14-006A
Figure 6. I/O Cell Block Diagram
D
Q
IO C R e g is te r
Q = D after rising edge of clo ck
holds until next rising ed ge
L
Q
IO C L a tc h
Q = L when clock is high
holds value when clock is low
08-14-007A
Figure 7. IOC Register Configurations
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the LCCs
in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-state
buffer and an output polarity control. The register/ latch can
be clocked from a variety of sources determined by the global
cell. It can also be bypassed for a non-registered input. The
combination of LCC and IOC allows for multiple buried
registers and logic paths. (See Figure 8).
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
3
04-02-051B
Commercial/Industrial
G roup A & B
Q
D
Input with optiona l
register/latch
CLK1
MUX
LC C C locks
I/O
C LK 2
MUX
PCLK
IO C C locks
I/O with
independe nt
output en able
1
A
B
C
D
OE
08-14 -008A
D
Q
R eg-T y pe
P res et
R es et
LC C R eg-T ype
LC C P resets
LC C R esets
G lobal C ell: LC C & IO C
2
08-14-009A
Figure 9. Global Cells
Figure 8. LCC & IOC With Two Outputs
Global Cells
The global cells, shown in Figure 9, are used to direct
global clock signals and/or control terms to the LCCs and
IOCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for IOC clocks
enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 10). The PA7540 provides two
global cells that divides the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
R e g is te r T yp e C h a ng e F e a tu re
R eg-T ype from G lobal C ell
D
P
Q
R
G lobal C ell can dynamica lly change user-
se lected LC C registers fro m D to T or from D
to JK . T his saves product terms for loadable
co unters or state machine s. U se as D register
to load, use as T or JK to count. T iming allows
dy namic operation.
T
P
E x a m p le :
P roduct terms for 10 bit lo adable binary counter
Q
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D /T uses 20 product term s (10 count, 10 load)
R
08-14-010A
Figure 10. Register Type Change Feature
internal signals to be simulated and analyzed via a
waveform display.(See Figures 10a-c)
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
ICT and manufacturers of popular development tools. ICT
offers the powerful PLACE Development Software (free to
qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE-
reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without
4
04-02-051B
Commercial/Industrial
waste. Programming of PEEL™ Arrays is supported by
many popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 12 - PLACE LCC and IOC screen
Figure 11 - PLACE Architectural Editor for
PA7540
Figure 13 - PLACE waveform and simulator
screen
5
04-02-051B
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
