NCP1631
Interleaved, 2-Phase Power
Factor Controller
The NCP1631 integrates a dual MOSFET driver for interleaved
PFC applications. Interleaving consists of paralleling two small
stages in lieu of a bigger one, more difficult to design. This approach
has several merits like the ease of implementation, the use of smaller
components or a better distribution of the heating.
Also, Interleaving extends the power range of Critical Conduction
Mode that is an efficient and cost−effective technique (no need for
low t
rr
diodes). In addition, the NCP1631 drivers are 180° phase shift
for a significantly reduced current ripple.
Housed in a SOIC16 package, the circuit incorporates all the
features necessary for building robust and compact interleaved PFC
stages, with a minimum of external components.
General Features
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MARKING DIAGRAM
NCP1631G
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
A
WL
Y
WW
G
•
Near−Unity Power Factor
•
Substantial 180° Phase Shift in All Conditions Including Transient
•
•
•
•
•
•
•
•
•
Phases
Frequency Clamped Critical Conduction Mode (FCCrM) i.e.,
Fixed Frequency, Discontinuous Conduction Mode Operation with
Critical Conduction Achievable in Most Stressful Conditions
FCCrM Operation Optimizes the PFC Stage Efficiency Over the
Load Range
Out−of−phase Control for Low EMI and a Reduced rms Current in
the Bulk Capacitor
Frequency Fold−back at Low Power to Further Improve the Light
Load Efficiency
Accurate Zero Current Detection by Auxiliary Winding for Valley
Turn On
Fast Line / Load Transient Compensation
High Drive Capability: −500 mA / +800 mA
Signal to Indicate that the PFC is Ready for Operation (“pfcOK”
Pin)
V
CC
Range: from 10 V to 20 V
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
ZCD2
FB
Rt
OSC
Vcontrol
FFOLD
BO
OVP / UVP
(Top View)
1
ZCD1
REF5V/pfcOK
DRV1
GND
Vcc
DRV2
Latch
CS
ORDERING INFORMATION
Device
NCP1631DR2G
Package
SOIC−16
(Pb−Free)
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Safety Features
•
Output Over and Under Voltage Protection
•
Brown−Out Detection with a 50−ms Delay to Help
•
•
•
•
Meet Hold−up Time Specifications
Soft−Start for Smooth Start−up Operation
Programmable Adjustment of the Maximum Power
Over Current Limitation
Detection of Inrush Currents
Typical Applications
•
Computer Power Supplies
•
LCD / Plasma Flat Panels
•
All Off Line Appliances Requiring Power Factor
Correction
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2016
1
March, 2016 − Rev. 7
Publication Order Number:
NCP1631/D
NCP1631
Vin
Vout
R
bo1
R
ovp1
R
out1
R
out2
OVP
in
Ac lin e
EMI
Filter
C
osc
C
comp2
R
comp1
R
t
R
FF
V
aux2
R
zcd2
1
2
3
4
5
R
bo2
R
ovp2
6
7
8
OVP
in
16 R
zcd1
15
14
13
12
11
10
9
R
ocp
R
CS
I
in
C
bulk
Vcc
pfcOK
M
1
M
2
D
2
LOAD
I
coil1
L
1
D
1
V
aux2
I
coil2
Vout
L
2
C
bo2
C
comp1
Cin
Figure 1. Typical Application Schematic
Table 1. MAXIMUM RATINGS
Symbol
V
CC(MAX)
V
MAX
Rating
Maximum Power Supply Voltage Continuous
Maximum Input Voltage on Low Power Pins
Pin
12
1, 2, 3, 4, 6, 7,
8, 9, 10, 15,
and 16
5
Value
−0.3, +20
−0.3, +9.0
Unit
V
V
V
Control(MAX)
P
D
R
qJ−A
T
J
T
J(MAX)
T
S(MAX)
T
L(MAX)
V
Control
Pin Maximum Input Voltage
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ T
A
= 70°C
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
ESD Capability, HBM model (Note 2)
ESD Capability, Machine Model (Note 2)
−0.3, V
Control(clamp)
(Note 1)
550
145
−55 to +150
150
−65 to +150
300
3
250
V
mW
°C/W
°C
°C
°C
°C
kV
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. “V
Control(clamp)
” is the pin5 clamp voltage.
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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2
NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE
(Conditions: V
CC
= 15 V, V
pin7
= 2 V, V
pin10
= 0 V; for typical
values T
J
= 25°C, for min/max values T
J
= −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis V
CC(on)
– V
CC(off)
Internal Logic Reset
Startup current
Supply Current
Device Enabled/No output load on pin6
Current that discharges V
CC
in latch mode
Current that discharges V
CC
in OFF
mode
OSCILLATOR AND FREQUENCY FOLDBACK
Clamping Charging Current
Pin 6 open
T
J
= −40°C to +125°C
T
J
= −55°C to +125°C (Note 6)
Pin 6 grounded
T
J
= −40°C to +125°C
T
J
= −55°C to +125°C (Note 6)
I
pin6
= 50
mA
Pin 6 grounded
T
J
= −40°C to +125°C
T
J
= −55°C to +125°C (Note 6)
I
pin6
= 50
mA
I
pin6
= 50
mA,
V
pin5
= 2.5 V
I
OSC(clamp)
31.5
30
I
OSC(CH1)
126
120
I
OSC(CH2)
I
OSC(DISCH1)
94.5
90
I
OSC(DISCH2)
V
FF
V
OSC(high)
V
OSC(low)
V
OSC(swing)
45
0.9
−
3.6
0.93
105
105
50
1.0
5
4.0
0.98
115.5
115.5
55
1.3
−
4.4
1.03
mA
V
V
V
V
76.5
140
140
85
154
154
93.5
mA
mA
35
35
38.5
38.5
mA
mA
V
V
CC
increasing
V
CC
decreasing
V
CC
decreasing
V
CC
= 9.4 V
F
sw
= 130 kHz (Note 4)
V
CC
= 15 V, V
pin10
= 5 V
V
CC
= 15 V, pin 7 grounded
V
CC(on)
V
CC(off)
V
CC(hyst)
V
CC(reset)
I
CC(start)
I
CC1
I
CC(latch)
I
CC(off)
11
9.5
1.5
4.0
−
−
–
−
11.85
10
1.85
5.75
35
5.0
0.4
0.4
12.7
10.5
−
7.5
100
7.0
0.8
0.8
mA
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
Charge Current with no frequency foldback
Charge Current @ I
pin6
= 50
mA
Maximum Discharge Current
with no frequency foldback
Discharge Current @ I
pin6
= 50
mA
Voltage on pin 6
Oscillator Upper Threshold
Oscillator Lower Threshold
Oscillator Swing (Note 5)
CURRENT SENSE
Current Sense Voltage Offset
Current Sense Protection Threshold
I
pin9
= 100
mA
I
pin9
= 10
mA
T
J
= 25°C
T
J
= −40°C to 125°C
T
J
= −55°C to +125°C (Note 6)
T
J
= −40°C to +125°C
T
J
= −55°C to +125°C
V
CS(TH100)
V
CS(TH10)
I
ILIM1
−20
−10
202
194
173
11
10.4
0
0
210
210
210
14
14
20
10
226
226
226
17
17
mV
mA
Threshold for In−rush Current Detection
(Note 5)
GATE DRIVE
Drive Resistance
DRV1 Sink
DRV1 Source
DRV2 Sink
DRV2 Source
I
in−rush
mA
Ω
I
pin14
= 100 mA
I
pin14
= −100 mA
I
pin11
= 100 mA
I
pin11
= −100 mA
R
SNK1
R
SRC1
R
SNK2
R
SRC2
–
–
–
–
7
15
7
15
15
25
15
25
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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3
NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE
(Conditions: V
CC
= 15 V, V
pin7
= 2 V, V
pin10
= 0 V; for typical
values T
J
= 25°C, for min/max values T
J
= −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
GATE DRIVE
Drive Current Capability (Note 5)
DRV1 Sink
DRV1 Source
DRV2 Sink
DRV2 Source
Rise Time
DRV1
DRV2
Fall Time
DRV1
DRV2
REGULATION BLOCK
Feedback Voltage Reference
Error Amplifier Source Current Capability
Error Amplifier Sink Current Capability
Error Amplifier Gain
Pin 5 Source Current when (V
out(low)
Detect) is activated
Pin2 Bias Current
Pin 5 Voltage:
T
J
= −40°C to 125°C
T
J
= −55°C to +125°C (Note 6)
V
pin2
= 2.5 V
@ V
pin2
= 2.4 V
@ V
pin2
= 2.6 V
@ V
pin2
= 2.6 V, I
pin6
= 90
mA
@ V
pin2
= 2.4 V, I
pin6
= 90
mA
FB falling
FB rising
@ V
pin2
= 2.4 V
@ V
pin2
= 2.6 V
V
REF
I
EA(SRC)
I
EA(SNK)
G
EA
I
Control(boost)
I
FB(bias)
V
Control(clamp)
V
Control(MIN)
V
Control(range)
V
REGUL(MIN)
V
REGUL(Clamp)
V
out(low)
/V
REF
H
out(low)
/V
REF
110
184
178
−500
3.0
0
2.7
−
−
95.0
−
3.6
0.6
3
−
1.66
95.5
−
2.44
2.500
−20
+20
200
230
230
290
276
276
500
4.2
1.2
3.3
0.1
−
96.0
0.5
mS
mA
mA
nA
V
2.56
V
mA
mA
V
DRV1
= 10 V
V
DRV1
= 0 V
V
DRV2
= 10 V
V
DRV2
= 0 V
C
DRV1
= 1 nF, V
DRV1
= 1 to 10 V
C
DRV2
= 1 nF, V
DRV2
= 1 to 10 V
C
DRV1
= 1 nF, V
DRV1
= 10 to 1 V
C
DRV2
= 1 nF, V
DRV2
= 10 to 1 V
I
SNK1
I
SRC1
I
SNK1
I
SRC1
t
r1
t
r2
t
f1
t
f2
−
−
−
−
−
−
–
–
800
500
800
500
40
40
20
20
−
−
−
−
ns
−
−
ns
–
–
Test Conditions
Symbol
Min
Typ
Max
Unit
Internal V
REGUL
Voltage
(measured on pin 6):
Ratio (V
out(low)
Detect Threshold / V
REF
)
(Note 5)
Ratio (V
out(low)
Detect Hysteresis /
V
REF
) (Note 5)
SKIP MODE
Duty Cycle
RAMP CONTROL (valid for the two phases)
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
T
J
= −25°C to +125°C
V
%
%
V
pin2
= 3 V
D
MIN
−
−
0
%
V
pin7
= 1.1 V, I
pin3
= 50
mA
V
pin7
= 1.1 V, I
pin3
= 200
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 100
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 400
mA
(Note 5)
V
pin7
= 1.1 V, I
pin3
= 50
mA
V
pin7
= 1.1 V, I
pin3
= 200
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 100
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 400
mA
(Note 5)
V
pin7
= 1.1 V, I
pin3
= 50
mA
(Note 6)
V
pin7
= 1.1 V, I
pin3
= 200
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 100
mA
(Note 5)
V
pin7
= 2.2 V, I
pin3
= 400
mA
(Note 5)
t
on1
t
on2
t
on3
t
on4
t
on1
t
on2
t
on3
t
on4
t
on1
t
on2
t
on3
t
on4
14.5
1.10
4.00
0.35
14.0
1.05
3.84
0.33
13.0
1.00
3.70
0.32
19.5
1.35
5.00
0.41
19.5
1.35
5.00
0.41
19.5
1.35
5.00
0.41
22.5
1.60
6.00
0.48
22.5
1.60
6.00
0.48
22.5
1.60
6.00
0.48
ms
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
T
J
= −40°C to +125°C
ms
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
T
J
= −55°C to +125°C
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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4
NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE
(Conditions: V
CC
= 15 V, V
pin7
= 2 V, V
pin10
= 0 V; for typical
values T
J
= 25°C, for min/max values T
J
= −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
RAMP CONTROL (valid for the two phases)
Pin 3 voltage
V
BO
= V
pin7
= 1.1 V, I
pin3
= 50
mA
V
BO
= V
pin7
= 1.1 V, I
pin3
= 200
mA
V
BO
= V
pin7
= 2.2 V, I
pin3
= 50
mA
V
BO
= V
pin7
= 2.2 V, I
pin3
= 200
mA
Not tested
V
Rt1
V
Rt2
V
Rt3
V
Rt4
V
ton(MAX)
I
Rt(MAX)
I
Rt(off)
Not tested
I
Rt(range)
20
1
1.071
1.071
2.169
2.169
1.096
1.096
2.196
2.196
5
−
7
1000
−
1.121
1.121
2.223
2.223
V
Test Conditions
Symbol
Min
Typ
Max
Unit
Maximum V
ton
Voltage
Pin 3 Current Capability
Pin 3 sourced current below which the
controller is OFF
Pin 3 Current Range
V
mA
mA
mA
ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2)
ZCD Threshold Voltage
ZCD Hysteresis
Input Clamp Voltage
High State
Low State
Internal Input Capacitance (Note 5)
ZCD Watchdog Delay
BROWN−OUT DETECTION
Brown−Out Comparator Threshold
Brown−Out Current Source
Brown−Out Blanking Time (Note 5)
Brown−Out Monitoring Window (Note 5)
Pin 7 clamped voltage if V
BO
< V
BO(TH)
during t
BO(BLANK)
Current Capability of the BO Clamp
Hysteresis V
BO(TH)
– V
BO(clamp)
Current Capability of the BO pin Clamp
PNP Transistor
Pin BO voltage when clamped by the PNP
OVER AND UNDER VOLTAGE PROTECTIONS
Over−Voltage Protection Threshold
Ratio (V
OVP
/ V
REF
) (Note 5)
Ratio UVP Threshold over V
REF
Pin 8 Bias Current
LATCH INPUT
Pin Latch Threshold for Shutdown
V
Latch
2.375
2.500
2.625
V
V
pin8
= 2.5 V
V
pin8
= 0.3 V
V
OVP
V
OVP
/V
REF
V
UVP
/V
REF
I
OVP(bias)
2.425
99.2
8
−500
2.500
99.7
12
−
2.575
100.2
16
500
V
%
%
nA
I
pin7
= − 100
mA
I
pin7
= − 100
mA
I
pin7
= −100
mA
T
J
= −40°C to 125°C
T
J
= −55°C to +125°C (Note 6)
T
J
= −40°C to 125°C
T
J
= −55°C to +125°C
V
BO(TH)
I
BO
t
BO(BLANK)
t
BO(window)
V
BO(clamp)
I
BO(clamp)
V
BO(HYS)
I
BO(PNP)
V
BO(PNP)
0.97
6
5.7
38
38
38
−
100
10
100
0.35
1.00
7
7
50
50
50
965
−
35
−
0.70
1.03
8
8
62
63.5
62
−
−
60
−
0.90
V
mA
ms
ms
mV
mA
mV
mA
V
V
ZCD
increasing
V
ZCD
falling
V
ZCD
decreasing
I
pin1
= 5.0 mA
I
pin1
= −5.0 mA
V
ZCD(TH),H
V
ZCD(TH),L
V
ZCD(HYS)
V
ZCD(high)
V
ZCD(low)
C
ZCD
t
ZCD
9.0
−1.1
−
80
0.40
0.20
0.50
0.25
0.25
11
−0.65
10
200
13
−0.1
−
320
pF
ms
0.60
0.30
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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5
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