CAT5172
256‐position SPI
Compatible Digital
Potentiometer (POT)
The CAT5172 is a 256-position digital linear taper potentiometer
ideally suited for replacing mechanical potentiometers and variable
resistors. Like mechanical potentiometers, the CAT5172 has a
resistive element, which can span V
CC
to Ground or float anywhere
between the power supply rails.
Wiper settings are controlled through an SPI-compatible digital
interface. Upon power-up, the wiper assumes a mid-span position and
may be repositioned anytime after the power is stable.
The CAT5172 operates from 2.7 V to 5.5 V, while consuming less
than 2
mA.
This low operating current, combined with a small package
footprint, make the CAT5172 ideal for battery-powered portable
appliance.
Features
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SOT23−8
TB SUFFIX
CASE 527AK
MARKING DIAGRAM
256-position
End-to-End Resistance: 50 kW, 100 kW
SPI Compatible Interface
Power-on Preset to Midscale
Single Supply 2.7 V to 5.5 V
Low Temperature Coefficient 100 ppm/C
Low Power, I
DD
2
mA
max
Wide Operating Temperature
−40C
to +85C
SOT−23 8-lead (2.9 mm
3 mm) Package
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
ADYM
1
1
AEYM
AD = 50 kW
AE = 100 kW
Y = Production Year
Y =
(Last Digit)
M = Production Month
M =
(1
−
9, A, B, C)
Typical Applications
Potentiometer Replacement
Transducer Adjustment of Pressure, Temperature, Position,
Chemical, and Optical Sensors
RF Amplifier Biasing
Gain Control and Offset Adjustment
PIN CONNECTIONS
W
V
DD
GND
CLK
(Top View)
1
A
B
CS
SDI
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 1
1
Publication Order Number:
CAT5172/D
CAT5172
V
DD
CS
SDI
CLK
SPI
INTERFACE
A
W
WIPER
REGISTER
GND
B
Figure 1. Functional Block Diagram
Table 1. ORDERING INFORMATION
Part Number
CAT5172TBI−50GT3
CAT5172TBI−00GT3
Resistance
50 kW
100 kW
Temperature Range
−40C
to 85C
Package
SOT−23−8
(Pb−Free)
Shipping
†
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
Pin Name
W
V
DD
GND
CLK
SDI
CS
B
A
Resistor’s Wiper Terminal.
Positive Power Supply.
Digital Ground.
Serial Clock Input. Positive edge triggered.
Serial Data Input.
Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register.
Bottom Terminal of resistive element.
Top Terminal of resistive element.
Description
Table 3. ABSOLUTE MAXIMUM RATINGS
(Note 2)
Rating
V
DD
to GND
V
A
, V
B
, V
W
to GND
I
MAX
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
JMAX
)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Value
−0.3
to 6.5
V
DD
20
0 to 6.5
−40
to +85
150
−65
to +150
300
mA
V
C
C
C
C
Unit
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and
maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
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CAT5172
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
V
DD
= 5 V
10%,
or 3 V
10%;
V
A
= V
DD
; V
B
= 0 V; –40C < T
A
< +85C; unless otherwise noted.
Parameter
DC CHARACTERISTICS
−
RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 4)
Resistor Integral Nonlinearity (Note 4)
Nominal Resistor Tolerance (Note 5)
Resistance Temperature Coefficient
Wiper Resistance
R
WB
, V
A
= no connection
R
WB
, V
A
= no connection
T
A
= 25C
V
AB
= V
DD
, Wiper = no connection
V
DD
= 5 V
V
DD
= 3 V
DC CHARACTERISTICS
−
POTENTIOMETER DIVIDER MODE
Resolution
Differential Nonlinearity (Note 6)
Integral Nonlinearity (Note 6)
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range (Note 7)
Capacitance (Note 8) A, B
Capacitance (Note 8) W
Common-Mode Leakage (Note 8)
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance (Note 8)
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation (Note 9)
Power Supply Sensitivity
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
nV
DD
= +5 V
10%,
Code = Midscale
V
DD RANGE
I
DD
P
DISS
PSS
2.7
0.3
5.5
2
0.2
0.05
V
mA
mW
%/%
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
5
0.7 x V
DD
0.3V
DD
1
0.7 x V
DD
0.3V
DD
V
V
V
V
mA
pF
f = 1 MHz, measured to GND,
Code = 0 x 80
f = 1 MHz, measured to GND,
Code = 0 x 80
V
A
= V
B
= V
DD
/2
V
A,B,W
C
A,B
C
W
I
CM
GND
45
60
1
V
DD
V
pF
pF
nA
Code = 0x80
Code = 0xFF
Code = 0x00
N
DNL
INL
nV
W
/nT
V
WFSE
V
WZSE
−3
0
−1
−1
0.1
0.4
100
−1
1
0
3
8
+1
+1
Bits
LSB
LSB
ppm/C
LSB
LSB
R−DNL
R−INL
nR
AB
nR
AB
/nT
R
W
−1
−2
−20
100
50
100
120
250
0.1
0.4
+1
+2
+20
LSB
LSB
%
ppm/C
W
Test Conditions
Symbol
Min
Typ
(Note 3)
Max
Unit
3. Typical specifications represent average readings at +25C and V
DD
= 5 V.
4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are
guaranteed monotonic.
5. V
AB
= V
DD
, Wiper (V
W
) = no connect.
6. INL and DNL are measured at VW with the digital POT configured as a potentiometer divider similar to a voltage output D/A converter.
V
A
= V
DD
and V
B
= 0 V. DNL specification limits of
1
LSB maximum are guaranteed monotonic operating conditions.
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8. Guaranteed by design and not subject to production test.
9. PDISS is calculated from (I
DD
x V
DD
). CMOS logic level inputs result in minimum power dissipation.
10. All dynamic characteristics use V
DD
= 5 V.
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CAT5172
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
(continued)
V
DD
= 5 V
10%,
or 3 V
10%;
V
A
= V
DD
; V
B
= 0 V; –40C < T
A
< +85C; unless otherwise noted.
Parameter
DYNAMIC CHARACTERISTICS
(Notes 8 and 10)
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time (50 kW/100 kW)
R
AB
= 50 kW / 100 kW, Code = 0x80
V
A
=1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 kW
V
A
= 5 V, V
B
= 0 V,
1
LSB error band
BW
THD
W
t
S
100/40
0.05
2
kHz
%
ms
Test Conditions
Symbol
Min
Typ
(Note 3)
Max
Unit
3. Typical specifications represent average readings at +25C and V
DD
= 5 V.
4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are
guaranteed monotonic.
5. V
AB
= V
DD
, Wiper (V
W
) = no connect.
6. INL and DNL are measured at VW with the digital POT configured as a potentiometer divider similar to a voltage output D/A converter.
V
A
= V
DD
and V
B
= 0 V. DNL specification limits of
1
LSB maximum are guaranteed monotonic operating conditions.
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8. Guaranteed by design and not subject to production test.
9. PDISS is calculated from (I
DD
x V
DD
). CMOS logic level inputs result in minimum power dissipation.
10. All dynamic characteristics use V
DD
= 5 V.
Table 5. TIMING CHARACTERISTICS: 50 kW and 100 kW Versions
V
DD
= 5 V
10%, or 3 V
10%; V
A
= V
DD
; V
B
= 0 V; –40C < T
A
< +85C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
(Note 11)
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS
(Notes 12 and 13)
(Specifications Apply to All Parts)
Clock Frequency
Input Clock Pulse width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Clock level high or low
f
CLK
t
CH
, t
CL
t
DS
t
DH
T
CSS
T
CSW
T
CSH0
T
CSH1
T
CS1
20
5
5
15
40
0
0
10
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
11. Typical specifications represent average readings at +25C and V
DD
= 5 V.
12. Guaranteed by design and not subject to production test.
13. See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V.
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CAT5172
SPI INTERFACE
Table 6. CAT5172 SERIAL DATA−WORD FORMAT
B7
D7
MSB
2
7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
LSB
2
0
CS
1
CLK
DATA IN
SDI
V1
V2
D7 D6 D5 D4 D3 D2 D1 D0
2
3
4
5
6
7
8
V
OUT
Figure 2. CAT5172 SPI Interface Timing Diagram (V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
1
SDI
(DATA IN) 0
CLK
t
CSHO
CS
1
0
1
0
Dx
t
CH
Dx
t
DS
t
DH
t
CS1
t
CSH1
t
CSS
t
CL
t
CSW
t
S
VOUT
V
W
V
W0
1
LSB
Figure 3. SPI Interface Detailed Timing Diagram (V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
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